membarriers.h

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/*
 * Copyright (c) 2023 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
 */
 
#include <zephyr/kernel.h>
#include <nrfx.h>
 
static inline void cmb(void)
{
        /* The Data Memory Barrier (DMB) instruction ensures that
         * outstanding memory transactions complete before subsequent
         * memory transactions. It is expected to be defined by cmsis.h.
         */
        __DMB();
}
 
static inline void wmb(void)
{
#ifdef __aarch64__
        __asm__ volatile("dsb sy;" ::: "memory");
#elif defined(__amd64__)
        __asm__ volatile("sfence;" ::: "memory");
#else
        /* CUSTOMIZATION: implement CPU specific memory barrier if it has any.
         * Use at least a compiler memory barrier.
         */
 
        /* Cortex-M33 does not support wmb, but cmb/DMB is more
         * restrictive and therefore safe to use.
         */
        cmb();
#endif
}
 
static inline void rmb(void)
{
#ifdef __aarch64__
        __asm__ volatile("dsb sy;" ::: "memory");
#elif defined(__amd64__)
        __asm__ volatile("lfence;" ::: "memory");
#else
        /* CUSTOMIZATION: implement CPU specific memory barrier if it has any.
         * Use at least a compiler memory barrier.
         */
 
        /* Cortex-M33 does not support rmb, but cmb/DMB is more
         * restrictive and therefore safe to use.
         */
        cmb();
#endif
}