doxygen/html/nrf__sp__can_8h_source.html

/*

 * Copyright (c) 2025 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

 */


#ifndef NRF_SP_CAN_H__

#define NRF_SP_CAN_H__


#ifdef __cplusplus

extern "C" {

#endif


#include "nrfx.h"                                     // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc.


/* ===========================================================================================================================

 * ================                                          SP_CAN                                          ================

 * ===========================================================================================================================*/


#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)

/* ================================================== Struct SP_CAN_CONFIG =================================================== */


typedef struct

{

    __IOM uint32_t PARSING;

    __IOM uint32_t TIMING;

    __IOM uint32_t REQUEST;

    __IOM uint32_t MODE;

} NRF_SP_CAN_CONFIG_Type;

/* SP_CAN_CONFIG_PARSING: SCAN parsing options */

  #define SP_CAN_CONFIG_PARSING_ResetValue (0x00000000UL)

/* REGGROUP @Bits 0..2 : Which register group to parse */

  #define SP_CAN_CONFIG_PARSING_REGGROUP_Pos           (0UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_Msk           (0x7UL << SP_CAN_CONFIG_PARSING_REGGROUP_Pos)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_Min           (0x0UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_Max           (0x3UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_None          (0x0UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_Timing        (0x1UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_OperationMode (0x2UL)

  #define SP_CAN_CONFIG_PARSING_REGGROUP_RxFilters     (0x3UL)

/* SP_CAN_CONFIG_TIMING: SCAN Timing parameters */

  #define SP_CAN_CONFIG_TIMING_ResetValue (0x00000000UL)

/* RSYNCJUMPWIDTH @Bits 0..7 : Re-synchronization jump width */

  #define SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Pos    (0UL)


  #define SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Msk                                                        \

                                                     (0xFFUL << SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Pos) \


/* PHASESEG1 @Bits 8..15 : Number of time quanta in phase 1 */

  #define SP_CAN_CONFIG_TIMING_PHASESEG1_Pos (8UL)

  #define SP_CAN_CONFIG_TIMING_PHASESEG1_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PHASESEG1_Pos)

/* PHASESEG2 @Bits 16..23 : Number of time quanta in phase 2 */

  #define SP_CAN_CONFIG_TIMING_PHASESEG2_Pos (16UL)

  #define SP_CAN_CONFIG_TIMING_PHASESEG2_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PHASESEG2_Pos)

/* PRESCALER @Bits 24..31 : Data Bit Rate Prescaler */

  #define SP_CAN_CONFIG_TIMING_PRESCALER_Pos (24UL)

  #define SP_CAN_CONFIG_TIMING_PRESCALER_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PRESCALER_Pos)

/* SP_CAN_CONFIG_REQUEST: (unspecified) */

  #define SP_CAN_CONFIG_REQUEST_ResetValue (0x00000000UL)

/* REQUEST @Bit 0 : Request either TX or RX */

  #define SP_CAN_CONFIG_REQUEST_REQUEST_Pos (0UL)

  #define SP_CAN_CONFIG_REQUEST_REQUEST_Msk (0x1UL << SP_CAN_CONFIG_REQUEST_REQUEST_Pos)

  #define SP_CAN_CONFIG_REQUEST_REQUEST_Min (0x0UL)

  #define SP_CAN_CONFIG_REQUEST_REQUEST_Max (0x1UL)

  #define SP_CAN_CONFIG_REQUEST_REQUEST_RX  (0x0UL)

  #define SP_CAN_CONFIG_REQUEST_REQUEST_TX  (0x1UL)

/* SP_CAN_CONFIG_MODE: Operation mode */

  #define SP_CAN_CONFIG_MODE_ResetValue (0x00000000UL)

/* MODE @Bits 0..1 : Operation mode */

  #define SP_CAN_CONFIG_MODE_MODE_Pos        (0UL)

  #define SP_CAN_CONFIG_MODE_MODE_Msk        (0x3UL << SP_CAN_CONFIG_MODE_MODE_Pos)

  #define SP_CAN_CONFIG_MODE_MODE_Min        (0x0UL)

  #define SP_CAN_CONFIG_MODE_MODE_Max        (0x3UL)

  #define SP_CAN_CONFIG_MODE_MODE_Normal     (0x0UL)

  #define SP_CAN_CONFIG_MODE_MODE_Loopback   (0x1UL)

  #define SP_CAN_CONFIG_MODE_MODE_ListenOnly (0x2UL)

  #define SP_CAN_CONFIG_MODE_MODE_OneShot    (0x3UL)

/* ================================================= Struct SP_CAN_RXFILTER ================================================== */


typedef struct

{

    __IOM uint32_t IDFILTER;

    __IOM uint32_t IDMASK;

} NRF_SP_CAN_RXFILTER_Type;


  #define SP_CAN_RXFILTER_MaxCount (4UL)

  #define SP_CAN_RXFILTER_MaxIndex (3UL)

  #define SP_CAN_RXFILTER_MinIndex (0UL)

/* SP_CAN_RXFILTER_IDFILTER: ID filter for RX */

  #define SP_CAN_RXFILTER_IDFILTER_ResetValue (0x00000000UL)

/* IDENTIFIER @Bits 0..28 : ID to match for RX */

  #define SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Pos    (0UL)


  #define SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Msk                                                              \

                                                     (0x1FFFFFFFUL << SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Pos) \


/* USEFILTER @Bit 29 : Enable the filter to match against a received message */

  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos         (29UL)


  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Msk                                                           \

                                                         (0x1UL << SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos) \


  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Min         (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Max         (0x1UL)

  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Disabled    (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Enabled     (0x1UL)

/* INMAILBOX @Bit 30 : sCAN driver has put the data in a mailbox */

  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos         (30UL)


  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Msk                                                           \

                                                         (0x1UL << SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos) \


  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Min         (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Max         (0x1UL)

  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Disabled    (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Enabled     (0x1UL)

/* FILTERMATCHED @Bit 31 : Indicates that the filter has been matched */

  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos        (31UL)


  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Msk                                                              \

                                                            (0x1UL << SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos) \


  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Min        (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Max        (0x1UL)

  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_NoMatch    (0x0UL)

  #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Match      (0x1UL)

/* SP_CAN_RXFILTER_IDMASK: ID mask filter for RX */

  #define SP_CAN_RXFILTER_IDMASK_ResetValue (0x00000000UL)

/* MASK @Bits 0..28 : ID mask filter for RX */

  #define SP_CAN_RXFILTER_IDMASK_MASK_Pos (0UL)

  #define SP_CAN_RXFILTER_IDMASK_MASK_Msk (0x1FFFFFFFUL << SP_CAN_RXFILTER_IDMASK_MASK_Pos)

/* ================================================== Struct SP_CAN_TXFRAME ================================================== */


typedef struct

{

    __IOM uint32_t IDENTIFIER;

    __IOM uint32_t TXDATAL;

    __IOM uint32_t TXDATAH;

    __IOM uint32_t METADATA;

} NRF_SP_CAN_TXFRAME_Type;


  #define SP_CAN_TXFRAME_MaxCount (4UL)

  #define SP_CAN_TXFRAME_MaxIndex (3UL)

  #define SP_CAN_TXFRAME_MinIndex (0UL)

/* SP_CAN_TXFRAME_IDENTIFIER: Frame Identifier */

  #define SP_CAN_TXFRAME_IDENTIFIER_ResetValue (0x00000000UL)

/* IDENTIFIER @Bits 0..28 : Frame Identifier */

  #define SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos    (0UL)


  #define SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Msk                                                               \

                                                      (0x1FFFFFFFUL << SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos) \


/* SP_CAN_TXFRAME_TXDATAL: TX data buffer LSB */

  #define SP_CAN_TXFRAME_TXDATAL_ResetValue (0x00000000UL)

/* TXDATA0 @Bits 0..7 : Data */

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA0_Pos (0UL)

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA0_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA0_Pos)

/* TXDATA1 @Bits 8..15 : Data */

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA1_Pos (8UL)

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA1_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA1_Pos)

/* TXDATA2 @Bits 16..23 : Data */

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA2_Pos (16UL)

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA2_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA2_Pos)

/* TXDATA3 @Bits 24..31 : Data */

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA3_Pos (24UL)

  #define SP_CAN_TXFRAME_TXDATAL_TXDATA3_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA3_Pos)

/* SP_CAN_TXFRAME_TXDATAH: TX data buffer MSB */

  #define SP_CAN_TXFRAME_TXDATAH_ResetValue (0x00000000UL)

/* TXDATA4 @Bits 0..7 : Data */

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA4_Pos (0UL)

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA4_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA4_Pos)

/* TXDATA5 @Bits 8..15 : Data */

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA5_Pos (8UL)

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA5_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA5_Pos)

/* TXDATA6 @Bits 16..23 : Data */

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA6_Pos (16UL)

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA6_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA6_Pos)

/* TXDATA7 @Bits 24..31 : Data */

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA7_Pos (24UL)

  #define SP_CAN_TXFRAME_TXDATAH_TXDATA7_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA7_Pos)

/* SP_CAN_TXFRAME_METADATA: Frame's metadata */

  #define SP_CAN_TXFRAME_METADATA_ResetValue (0x00000000UL)

/* EXTENDEDFORMAT @Bit 0 : Frame's IDE (Identifier Extension bit) */

  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos         (0UL)


  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Msk                                                               \

                                                             (0x1UL << SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos) \


  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Min         (0x0UL)

  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Max         (0x1UL)

  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Disabled    (0x0UL)

  #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Enabled     (0x1UL)

/* REMOTEREQUEST @Bit 1 : Frame's RTR (Remote Transmission request bit) */

  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos         (1UL)


  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Msk                                                              \

                                                            (0x1UL << SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos) \


  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Min         (0x0UL)

  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Max         (0x1UL)

  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Disabled    (0x0UL)

  #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Enabled     (0x1UL)

/* DATALENGTH @Bits 2..5 : Frame's DLC (Data Length Code) */

  #define SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos (2UL)

  #define SP_CAN_TXFRAME_METADATA_DATALENGTH_Msk (0xFUL << SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos)

/* CRC @Bits 16..30 : Frame's CRC */

  #define SP_CAN_TXFRAME_METADATA_CRC_Pos (16UL)

  #define SP_CAN_TXFRAME_METADATA_CRC_Msk (0x7FFFUL << SP_CAN_TXFRAME_METADATA_CRC_Pos)

/* ================================================== Struct SP_CAN_RXFRAME ================================================== */


typedef struct

{

    __IOM uint32_t IDENTIFIER;

    __IOM uint32_t RXDATAL;

    __IOM uint32_t RXDATAH;

    __IOM uint32_t METADATA;

} NRF_SP_CAN_RXFRAME_Type;


  #define SP_CAN_RXFRAME_MaxCount (4UL)

  #define SP_CAN_RXFRAME_MaxIndex (3UL)

  #define SP_CAN_RXFRAME_MinIndex (0UL)

/* SP_CAN_RXFRAME_IDENTIFIER: Frame Identifier */

  #define SP_CAN_RXFRAME_IDENTIFIER_ResetValue (0x00000000UL)

/* IDENTIFIER @Bits 0..28 : Frame Identifier */

  #define SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos    (0UL)


  #define SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Msk                                                               \

                                                      (0x1FFFFFFFUL << SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos) \


/* SP_CAN_RXFRAME_RXDATAL: RX data buffer LSB */

  #define SP_CAN_RXFRAME_RXDATAL_ResetValue (0x00000000UL)

/* RXDATA0 @Bits 0..7 : Data */

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA0_Pos (0UL)

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA0_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA0_Pos)

/* RXDATA1 @Bits 8..15 : Data */

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA1_Pos (8UL)

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA1_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA1_Pos)

/* RXDATA2 @Bits 16..23 : Data */

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA2_Pos (16UL)

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA2_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA2_Pos)

/* RXDATA3 @Bits 24..31 : Data */

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA3_Pos (24UL)

  #define SP_CAN_RXFRAME_RXDATAL_RXDATA3_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA3_Pos)

/* SP_CAN_RXFRAME_RXDATAH: RX data buffer MSB */

  #define SP_CAN_RXFRAME_RXDATAH_ResetValue (0x00000000UL)

/* RXDATA4 @Bits 0..7 : Data */

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA4_Pos (0UL)

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA4_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA4_Pos)

/* RXDATA5 @Bits 8..15 : Data */

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA5_Pos (8UL)

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA5_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA5_Pos)

/* RXDATA6 @Bits 16..23 : Data */

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA6_Pos (16UL)

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA6_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA6_Pos)

/* RXDATA7 @Bits 24..31 : Data */

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA7_Pos (24UL)

  #define SP_CAN_RXFRAME_RXDATAH_RXDATA7_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA7_Pos)

/* SP_CAN_RXFRAME_METADATA: Frame's metadata */

  #define SP_CAN_RXFRAME_METADATA_ResetValue (0x00000000UL)

/* EXTENDEDFORMAT @Bit 0 : Frame's IDE (Identifier Extension bit) */

  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos         (0UL)


  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Msk                                                               \

                                                             (0x1UL << SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos) \


  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Min         (0x0UL)

  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Max         (0x1UL)

  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Disabled    (0x0UL)

  #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Enabled     (0x1UL)

/* REMOTEREQUEST @Bit 1 : Frame's RTR (Remote Transmission request bit) */

  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos         (1UL)


  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Msk                                                              \

                                                            (0x1UL << SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos) \


  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Min         (0x0UL)

  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Max         (0x1UL)

  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Disabled    (0x0UL)

  #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Enabled     (0x1UL)

/* DATALENGTH @Bits 2..5 : Frame's DLC (Data Length Code) */

  #define SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos (2UL)

  #define SP_CAN_RXFRAME_METADATA_DATALENGTH_Msk (0xFUL << SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos)

/* CRC @Bits 16..30 : Frame's CRC */

  #define SP_CAN_RXFRAME_METADATA_CRC_Pos (16UL)

  #define SP_CAN_RXFRAME_METADATA_CRC_Msk (0x7FFFUL << SP_CAN_RXFRAME_METADATA_CRC_Pos)

/* ================================================== Struct SP_CAN_STATUS =================================================== */


typedef struct

{

    __IOM uint32_t STATUS;

} NRF_SP_CAN_STATUS_Type;

/* SP_CAN_STATUS_STATUS: SCAN status register */

  #define SP_CAN_STATUS_STATUS_ResetValue (0x80000000UL)

/* BITERROR @Bit 0 : Transmitter sends dominant/recessive but reads back recessive/dominant. Unable to transmit

 *                   dominant/recessive */


  #define SP_CAN_STATUS_STATUS_BITERROR_Pos (0UL)

  #define SP_CAN_STATUS_STATUS_BITERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BITERROR_Pos)

/* BITSTUFFINGERROR @Bit 1 : Receiver detects a sequence of 6 dominant or recessive bits */

  #define SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Pos    (1UL)


  #define SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Msk                                                         \

                                                       (0x1UL << SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Pos) \


/* FORMERROR @Bit 2 : Receiver detects a bit with invalid logical level in SOF/EOF fields or ACK/CRC delimiters */

  #define SP_CAN_STATUS_STATUS_FORMERROR_Pos (2UL)

  #define SP_CAN_STATUS_STATUS_FORMERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_FORMERROR_Pos)

/* ACKERROR @Bit 3 : Transmitter sends a message but ACK slot is not maide dominant by receiver(s) */

  #define SP_CAN_STATUS_STATUS_ACKERROR_Pos (3UL)

  #define SP_CAN_STATUS_STATUS_ACKERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_ACKERROR_Pos)

/* CRCERROR @Bit 4 : Receiver calculates a CRC that differs fomr the transmitted CRC field value */

  #define SP_CAN_STATUS_STATUS_CRCERROR_Pos (4UL)

  #define SP_CAN_STATUS_STATUS_CRCERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_CRCERROR_Pos)

/* BIT0ERROR @Bit 5 : Transmitter sends dominant but reads back recessive. Unable to transmit dominant */

  #define SP_CAN_STATUS_STATUS_BIT0ERROR_Pos (5UL)

  #define SP_CAN_STATUS_STATUS_BIT0ERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BIT0ERROR_Pos)

/* BIT1ERROR @Bit 6 : Transmitter sends recessive but reads back dominant. Unable to transmit recessive */

  #define SP_CAN_STATUS_STATUS_BIT1ERROR_Pos (6UL)

  #define SP_CAN_STATUS_STATUS_BIT1ERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BIT1ERROR_Pos)

/* PROTOCOLERROR @Bit 7 : Generic error response */

  #define SP_CAN_STATUS_STATUS_PROTOCOLERROR_Pos (7UL)

  #define SP_CAN_STATUS_STATUS_PROTOCOLERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_PROTOCOLERROR_Pos)

/* ARBITRATIONLOST @Bit 8 : TX attempt lost arbitration */

  #define SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Pos    (8UL)


  #define SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Msk                                                        \

                                                      (0x1UL << SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Pos) \


/* ARBITRATIONLOSTRXOK @Bit 9 : TX attempt lost arbitration, but there was a match for rx filter */

  #define SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Pos    (9UL)


  #define SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Msk                                                            \

                                                          (0x1UL << SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Pos) \


/* STATE @Bits 29..31 : sCAN state */

  #define SP_CAN_STATUS_STATUS_STATE_Pos          (29UL)

  #define SP_CAN_STATUS_STATUS_STATE_Msk          (0x7UL << SP_CAN_STATUS_STATUS_STATE_Pos)

  #define SP_CAN_STATUS_STATUS_STATE_Min          (0x0UL)

  #define SP_CAN_STATUS_STATUS_STATE_Max          (0x4UL)

  #define SP_CAN_STATUS_STATUS_STATE_ERRORACTIVE  (0x0UL)

  #define SP_CAN_STATUS_STATUS_STATE_ERRORWARNING (0x1UL)

  #define SP_CAN_STATUS_STATUS_STATE_ERRORPASSIVE (0x2UL)

  #define SP_CAN_STATUS_STATUS_STATE_BUSOFF       (0x3UL)

  #define SP_CAN_STATUS_STATUS_STATE_STOPPED      (0x4UL)

/* ================================================== Struct SP_CAN_SPSYNC =================================================== */


typedef struct

{

    __IOM uint32_t AUX[6];

} NRF_SP_CAN_SPSYNC_Type;

/* SP_CAN_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */

  #define SP_CAN_SPSYNC_AUX_MaxCount   (6UL)

  #define SP_CAN_SPSYNC_AUX_MaxIndex   (5UL)

  #define SP_CAN_SPSYNC_AUX_MinIndex   (0UL)

  #define SP_CAN_SPSYNC_AUX_ResetValue (0x00000000UL)

/* AUX @Bits 0..31 : Auxiliary register */

  #define SP_CAN_SPSYNC_AUX_AUX_Pos (0UL)

  #define SP_CAN_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << SP_CAN_SPSYNC_AUX_AUX_Pos)

/* ====================================================== Struct SP_CAN ====================================================== */


typedef struct

{

    __OM uint32_t                  TASKS_START;

    __OM uint32_t                  TASKS_RESET;

    __IOM uint32_t                 SUBSCRIBE_START;

    __IOM uint32_t                 SUBSCRIBE_RESET;

    __IOM uint32_t                 EVENTS_TXCOMPLETE;

    __IOM uint32_t                 EVENTS_RXCOMPLETE;

    __IOM uint32_t                 EVENTS_ERRORDETECTED;

    __IOM uint32_t                 EVENTS_STATECHANGED;

    __IOM uint32_t                 PUBLISH_TXCOMPLETE;

    __IOM uint32_t                 PUBLISH_RXCOMPLETE;

    __IOM uint32_t                 PUBLISH_ERRORDETECTED;

    __IOM uint32_t                 PUBLISH_STATECHANGED;

    __IOM uint32_t                 INTEN;

    __IOM uint32_t                 ENABLE;

    __IOM NRF_SP_CAN_CONFIG_Type   CONFIG;

    __IOM NRF_SP_CAN_RXFILTER_Type RXFILTER[4];

    __IOM NRF_SP_CAN_TXFRAME_Type  TXFRAME[4];

    __IOM NRF_SP_CAN_RXFRAME_Type  RXFRAME[4];

    __IOM NRF_SP_CAN_STATUS_Type   STATUS;

    __IOM NRF_SP_CAN_SPSYNC_Type   SPSYNC;

} NRF_SP_CAN_Type;

/* SP_CAN_TASKS_START: Trigger this task to start a request (RX/TX) */

  #define SP_CAN_TASKS_START_ResetValue (0x00000000UL)

/* TASKS_START @Bit 0 : Trigger this task to start a request (RX/TX) */

  #define SP_CAN_TASKS_START_TASKS_START_Pos     (0UL)

  #define SP_CAN_TASKS_START_TASKS_START_Msk     (0x1UL << SP_CAN_TASKS_START_TASKS_START_Pos)

  #define SP_CAN_TASKS_START_TASKS_START_Min     (0x1UL)

  #define SP_CAN_TASKS_START_TASKS_START_Max     (0x1UL)

  #define SP_CAN_TASKS_START_TASKS_START_Trigger (0x1UL)

/* SP_CAN_TASKS_RESET: Trigger this task to reset SCAN to UNINITIALIZED state */

  #define SP_CAN_TASKS_RESET_ResetValue (0x00000000UL)

/* TASKS_RESET @Bit 0 : Trigger this task to reset SCAN to UNINITIALIZED state */

  #define SP_CAN_TASKS_RESET_TASKS_RESET_Pos     (0UL)

  #define SP_CAN_TASKS_RESET_TASKS_RESET_Msk     (0x1UL << SP_CAN_TASKS_RESET_TASKS_RESET_Pos)

  #define SP_CAN_TASKS_RESET_TASKS_RESET_Min     (0x1UL)

  #define SP_CAN_TASKS_RESET_TASKS_RESET_Max     (0x1UL)

  #define SP_CAN_TASKS_RESET_TASKS_RESET_Trigger (0x1UL)

/* SP_CAN_SUBSCRIBE_START: Subscribe configuration for task START */

  #define SP_CAN_SUBSCRIBE_START_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */

  #define SP_CAN_SUBSCRIBE_START_CHIDX_Pos (0UL)

  #define SP_CAN_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SP_CAN_SUBSCRIBE_START_CHIDX_Pos)

  #define SP_CAN_SUBSCRIBE_START_CHIDX_Min (0x00UL)

  #define SP_CAN_SUBSCRIBE_START_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_SUBSCRIBE_START_EN_Pos      (31UL)

  #define SP_CAN_SUBSCRIBE_START_EN_Msk      (0x1UL << SP_CAN_SUBSCRIBE_START_EN_Pos)

  #define SP_CAN_SUBSCRIBE_START_EN_Min      (0x0UL)

  #define SP_CAN_SUBSCRIBE_START_EN_Max      (0x1UL)

  #define SP_CAN_SUBSCRIBE_START_EN_Disabled (0x0UL)

  #define SP_CAN_SUBSCRIBE_START_EN_Enabled  (0x1UL)

/* SP_CAN_SUBSCRIBE_RESET: Subscribe configuration for task RESET */

  #define SP_CAN_SUBSCRIBE_RESET_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that task RESET will subscribe to */

  #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Pos (0UL)

  #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << SP_CAN_SUBSCRIBE_RESET_CHIDX_Pos)

  #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Min (0x00UL)

  #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_SUBSCRIBE_RESET_EN_Pos      (31UL)

  #define SP_CAN_SUBSCRIBE_RESET_EN_Msk      (0x1UL << SP_CAN_SUBSCRIBE_RESET_EN_Pos)

  #define SP_CAN_SUBSCRIBE_RESET_EN_Min      (0x0UL)

  #define SP_CAN_SUBSCRIBE_RESET_EN_Max      (0x1UL)

  #define SP_CAN_SUBSCRIBE_RESET_EN_Disabled (0x0UL)

  #define SP_CAN_SUBSCRIBE_RESET_EN_Enabled  (0x1UL)

/* SP_CAN_EVENTS_TXCOMPLETE: This event signals that SCAN has completed a TX operation */

  #define SP_CAN_EVENTS_TXCOMPLETE_ResetValue (0x00000000UL)

/* EVENTS_TXCOMPLETE @Bit 0 : This event signals that SCAN has completed a TX operation */

  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Pos             (0UL)


  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Msk                                                                       \

                                                                     (0x1UL << SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Pos) \


  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Min             (0x0UL)

  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Max             (0x1UL)

  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_NotGenerated    (0x0UL)

  #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Generated       (0x1UL)

/* SP_CAN_EVENTS_RXCOMPLETE: This event signals that SCAN has finished RX after an ID match */

  #define SP_CAN_EVENTS_RXCOMPLETE_ResetValue (0x00000000UL)

/* EVENTS_RXCOMPLETE @Bit 0 : This event signals that SCAN has finished RX after an ID match */

  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Pos             (0UL)


  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Msk                                                                       \

                                                                     (0x1UL << SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Pos) \


  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Min             (0x0UL)

  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Max             (0x1UL)

  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_NotGenerated    (0x0UL)

  #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Generated       (0x1UL)

/* SP_CAN_EVENTS_ERRORDETECTED: This event signals that SCAN has detected an error. */

  #define SP_CAN_EVENTS_ERRORDETECTED_ResetValue (0x00000000UL)

/* EVENTS_ERRORDETECTED @Bit 0 : This event signals that SCAN has detected an error. */

  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Pos             (0UL)


  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Msk \

                                                                           (0x1UL << SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Pos)


  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Min             (0x0UL)

  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Max             (0x1UL)

  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_NotGenerated    (0x0UL)

  #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Generated       (0x1UL)

/* SP_CAN_EVENTS_STATECHANGED: This event signals that SCAN's state has changed. */

  #define SP_CAN_EVENTS_STATECHANGED_ResetValue (0x00000000UL)

/* EVENTS_STATECHANGED @Bit 0 : This event signals that SCAN's state has changed. */

  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Pos             (0UL)


  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Msk                                                                           \

                                                                         (0x1UL << SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Pos) \


  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Min             (0x0UL)

  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Max             (0x1UL)

  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_NotGenerated    (0x0UL)

  #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Generated       (0x1UL)

/* SP_CAN_PUBLISH_TXCOMPLETE: Publish configuration for event TXCOMPLETE */

  #define SP_CAN_PUBLISH_TXCOMPLETE_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that event TXCOMPLETE will publish to */

  #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Pos (0UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Pos)

  #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Min (0x00UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Pos      (31UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Msk      (0x1UL << SP_CAN_PUBLISH_TXCOMPLETE_EN_Pos)

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Min      (0x0UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Max      (0x1UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Disabled (0x0UL)

  #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Enabled  (0x1UL)

/* SP_CAN_PUBLISH_RXCOMPLETE: Publish configuration for event RXCOMPLETE */

  #define SP_CAN_PUBLISH_RXCOMPLETE_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that event RXCOMPLETE will publish to */

  #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Pos (0UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Pos)

  #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Min (0x00UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Pos      (31UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Msk      (0x1UL << SP_CAN_PUBLISH_RXCOMPLETE_EN_Pos)

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Min      (0x0UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Max      (0x1UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Disabled (0x0UL)

  #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Enabled  (0x1UL)

/* SP_CAN_PUBLISH_ERRORDETECTED: Publish configuration for event ERRORDETECTED */

  #define SP_CAN_PUBLISH_ERRORDETECTED_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that event ERRORDETECTED will publish to */

  #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Pos (0UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Pos)

  #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Min (0x00UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Pos      (31UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Msk      (0x1UL << SP_CAN_PUBLISH_ERRORDETECTED_EN_Pos)

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Min      (0x0UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Max      (0x1UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Disabled (0x0UL)

  #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Enabled  (0x1UL)

/* SP_CAN_PUBLISH_STATECHANGED: Publish configuration for event STATECHANGED */

  #define SP_CAN_PUBLISH_STATECHANGED_ResetValue (0x00000000UL)

/* CHIDX @Bits 0..7 : DPPI channel that event STATECHANGED will publish to */

  #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Pos (0UL)

  #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_STATECHANGED_CHIDX_Pos)

  #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Min (0x00UL)

  #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Max (0xFFUL)

/* EN @Bit 31 : (unspecified) */

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Pos      (31UL)

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Msk      (0x1UL << SP_CAN_PUBLISH_STATECHANGED_EN_Pos)

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Min      (0x0UL)

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Max      (0x1UL)

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Disabled (0x0UL)

  #define SP_CAN_PUBLISH_STATECHANGED_EN_Enabled  (0x1UL)

/* SP_CAN_INTEN: Enable or disable interrupt */

  #define SP_CAN_INTEN_ResetValue (0x00000000UL)

/* TXCOMPLETE @Bit 0 : Enable or disable interrupt for event TXATTEMPTCOMPLETE */

  #define SP_CAN_INTEN_TXCOMPLETE_Pos      (0UL)

  #define SP_CAN_INTEN_TXCOMPLETE_Msk      (0x1UL << SP_CAN_INTEN_TXCOMPLETE_Pos)

  #define SP_CAN_INTEN_TXCOMPLETE_Min      (0x0UL)

  #define SP_CAN_INTEN_TXCOMPLETE_Max      (0x1UL)

  #define SP_CAN_INTEN_TXCOMPLETE_Disabled (0x0UL)

  #define SP_CAN_INTEN_TXCOMPLETE_Enabled  (0x1UL)

/* RXCOMPLETE @Bit 1 : Enable or disable interrupt for event RXCOMPLETE */

  #define SP_CAN_INTEN_RXCOMPLETE_Pos      (1UL)

  #define SP_CAN_INTEN_RXCOMPLETE_Msk      (0x1UL << SP_CAN_INTEN_RXCOMPLETE_Pos)

  #define SP_CAN_INTEN_RXCOMPLETE_Min      (0x0UL)

  #define SP_CAN_INTEN_RXCOMPLETE_Max      (0x1UL)

  #define SP_CAN_INTEN_RXCOMPLETE_Disabled (0x0UL)

  #define SP_CAN_INTEN_RXCOMPLETE_Enabled  (0x1UL)

/* ERRORDETECTED @Bit 2 : Enable or disable interrupt for event ERRORDETECTED */

  #define SP_CAN_INTEN_ERRORDETECTED_Pos      (2UL)

  #define SP_CAN_INTEN_ERRORDETECTED_Msk      (0x1UL << SP_CAN_INTEN_ERRORDETECTED_Pos)

  #define SP_CAN_INTEN_ERRORDETECTED_Min      (0x0UL)

  #define SP_CAN_INTEN_ERRORDETECTED_Max      (0x1UL)

  #define SP_CAN_INTEN_ERRORDETECTED_Disabled (0x0UL)

  #define SP_CAN_INTEN_ERRORDETECTED_Enabled  (0x1UL)

/* STATECHANGED @Bit 3 : Enable or disable interrupt for event STATECHANGED */

  #define SP_CAN_INTEN_STATECHANGED_Pos      (3UL)

  #define SP_CAN_INTEN_STATECHANGED_Msk      (0x1UL << SP_CAN_INTEN_STATECHANGED_Pos)

  #define SP_CAN_INTEN_STATECHANGED_Min      (0x0UL)

  #define SP_CAN_INTEN_STATECHANGED_Max      (0x1UL)

  #define SP_CAN_INTEN_STATECHANGED_Disabled (0x0UL)

  #define SP_CAN_INTEN_STATECHANGED_Enabled  (0x1UL)

/* SP_CAN_ENABLE: Enable the SCAN peripheral */

  #define SP_CAN_ENABLE_ResetValue (0x00000000UL)

/* ENABLE @Bit 0 : Enable or disable SCAN */

  #define SP_CAN_ENABLE_ENABLE_Pos      (0UL)

  #define SP_CAN_ENABLE_ENABLE_Msk      (0x1UL << SP_CAN_ENABLE_ENABLE_Pos)

  #define SP_CAN_ENABLE_ENABLE_Min      (0x0UL)

  #define SP_CAN_ENABLE_ENABLE_Max      (0x1UL)

  #define SP_CAN_ENABLE_ENABLE_Disabled (0x0UL)

  #define SP_CAN_ENABLE_ENABLE_Enabled  (0x1UL)

#endif \


/* ========================================== End of section using anonymous unions ========================================== */

#endif /* NRF_SP_CAN_H */


NRF_SP_CAN_CONFIG_Type::MODE
__IOM uint32_t MODE
Definition nrf_sp_can.h:31

NRF_SP_CAN_CONFIG_Type::TIMING
__IOM uint32_t TIMING
Definition nrf_sp_can.h:29

NRF_SP_CAN_CONFIG_Type::PARSING
__IOM uint32_t PARSING
Definition nrf_sp_can.h:28

NRF_SP_CAN_CONFIG_Type::REQUEST
__IOM uint32_t REQUEST
Definition nrf_sp_can.h:30

NRF_SP_CAN_CONFIG_Type
CONFIG [SP_CAN_CONFIG] SCAN configuration.
Definition nrf_sp_can.h:27

NRF_SP_CAN_RXFILTER_Type::IDFILTER
__IOM uint32_t IDFILTER
Definition nrf_sp_can.h:99

NRF_SP_CAN_RXFILTER_Type::IDMASK
__IOM uint32_t IDMASK
Definition nrf_sp_can.h:100

NRF_SP_CAN_RXFILTER_Type
RXFILTER [SP_CAN_RXFILTER] sCAN RX filters.
Definition nrf_sp_can.h:98

NRF_SP_CAN_RXFRAME_Type::IDENTIFIER
__IOM uint32_t IDENTIFIER
Definition nrf_sp_can.h:259

NRF_SP_CAN_RXFRAME_Type::METADATA
__IOM uint32_t METADATA
Definition nrf_sp_can.h:262

NRF_SP_CAN_RXFRAME_Type::RXDATAH
__IOM uint32_t RXDATAH
Definition nrf_sp_can.h:261

NRF_SP_CAN_RXFRAME_Type::RXDATAL
__IOM uint32_t RXDATAL
Definition nrf_sp_can.h:260

NRF_SP_CAN_RXFRAME_Type
RXFRAME [SP_CAN_RXFRAME] sCAN frame configuration.
Definition nrf_sp_can.h:258

NRF_SP_CAN_SPSYNC_Type
SPSYNC [SP_CAN_SPSYNC] Registers used to acknowledge API function calls.
Definition nrf_sp_can.h:430

NRF_SP_CAN_STATUS_Type::STATUS
__IOM uint32_t STATUS
Definition nrf_sp_can.h:356

NRF_SP_CAN_STATUS_Type
STATUS [SP_CAN_STATUS] SCAN status.
Definition nrf_sp_can.h:355

NRF_SP_CAN_TXFRAME_Type::METADATA
__IOM uint32_t METADATA
Definition nrf_sp_can.h:165

NRF_SP_CAN_TXFRAME_Type::TXDATAH
__IOM uint32_t TXDATAH
Definition nrf_sp_can.h:164

NRF_SP_CAN_TXFRAME_Type::IDENTIFIER
__IOM uint32_t IDENTIFIER
Definition nrf_sp_can.h:162

NRF_SP_CAN_TXFRAME_Type::TXDATAL
__IOM uint32_t TXDATAL
Definition nrf_sp_can.h:163

NRF_SP_CAN_TXFRAME_Type
TXFRAME [SP_CAN_TXFRAME] sCAN frame configuration.
Definition nrf_sp_can.h:161

NRF_SP_CAN_Type::STATUS
__IOM NRF_SP_CAN_STATUS_Type STATUS
Definition nrf_sp_can.h:470

NRF_SP_CAN_Type::INTEN
__IOM uint32_t INTEN
Definition nrf_sp_can.h:464

NRF_SP_CAN_Type::EVENTS_RXCOMPLETE
__IOM uint32_t EVENTS_RXCOMPLETE
Definition nrf_sp_can.h:456

NRF_SP_CAN_Type::PUBLISH_STATECHANGED
__IOM uint32_t PUBLISH_STATECHANGED
Definition nrf_sp_can.h:463

NRF_SP_CAN_Type::ENABLE
__IOM uint32_t ENABLE
Definition nrf_sp_can.h:465

NRF_SP_CAN_Type::PUBLISH_ERRORDETECTED
__IOM uint32_t PUBLISH_ERRORDETECTED
Definition nrf_sp_can.h:462

NRF_SP_CAN_Type::PUBLISH_RXCOMPLETE
__IOM uint32_t PUBLISH_RXCOMPLETE
Definition nrf_sp_can.h:461

NRF_SP_CAN_Type::CONFIG
__IOM NRF_SP_CAN_CONFIG_Type CONFIG
Definition nrf_sp_can.h:466

NRF_SP_CAN_Type::EVENTS_ERRORDETECTED
__IOM uint32_t EVENTS_ERRORDETECTED
Definition nrf_sp_can.h:458

NRF_SP_CAN_Type::SPSYNC
__IOM NRF_SP_CAN_SPSYNC_Type SPSYNC
Definition nrf_sp_can.h:471

NRF_SP_CAN_Type::EVENTS_TXCOMPLETE
__IOM uint32_t EVENTS_TXCOMPLETE
Definition nrf_sp_can.h:454

NRF_SP_CAN_Type::SUBSCRIBE_RESET
__IOM uint32_t SUBSCRIBE_RESET
Definition nrf_sp_can.h:453

NRF_SP_CAN_Type::PUBLISH_TXCOMPLETE
__IOM uint32_t PUBLISH_TXCOMPLETE
Definition nrf_sp_can.h:460

NRF_SP_CAN_Type::TASKS_START
__OM uint32_t TASKS_START
Definition nrf_sp_can.h:450

NRF_SP_CAN_Type::TASKS_RESET
__OM uint32_t TASKS_RESET
Definition nrf_sp_can.h:451

NRF_SP_CAN_Type::SUBSCRIBE_START
__IOM uint32_t SUBSCRIBE_START
Definition nrf_sp_can.h:452

NRF_SP_CAN_Type::EVENTS_STATECHANGED
__IOM uint32_t EVENTS_STATECHANGED
Definition nrf_sp_can.h:459

NRF_SP_CAN_Type
Soft peripheral CAN.
Definition nrf_sp_can.h:449