nrf_sqspi.h

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/*
 * Copyright (c) 2025 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
 */
 
#ifndef NRF_SQSPI_H__
#define NRF_SQSPI_H__
 
#include "nrf_config_sqspi.h"
 
#ifdef __cplusplus
extern "C" {
#endif


typedef struct
{
    void * p_reg;        
    uint8_t
           drv_inst_idx; 
} nrf_sqspi_t;

typedef enum
{
    NRF_SQSPI_EVT_XFER_DONE,    
    NRF_SQSPI_EVT_XFER_STARTED, 
} nrf_sqspi_evt_type_t;

typedef enum
{
    NRF_SQSPI_RESULT_OK,      
    NRF_SQSPI_RESULT_ABORTED, 
} nrf_sqspi_evt_xfer_done_t;
 
typedef enum
{
    NRF_SQSPI_SUCCESS = 0,
    NRF_SQSPI_ERROR_BUSY,
    NRF_SQSPI_ERROR_UNSUPPORTED,
    NRF_SQSPI_ERROR_INVALID_PARAM,
    NRF_SQSPI_ERROR_INVALID_STATE,
    NRF_SQSPI_ERROR_HW_FAULT,
} nrf_sqspi_error_t;

typedef struct
{
    nrf_sqspi_evt_type_t type; 
 
    union
    {
        nrf_sqspi_evt_xfer_done_t
            xfer_done;         
    }                    data; 
} nrf_sqspi_evt_t;

typedef void (* nrf_sqspi_callback_t)(nrf_sqspi_t const * p_qspi,
                                      nrf_sqspi_evt_t *   p_event,
                                      void *              p_context);

typedef struct
{
    uint32_t sck;    
    uint32_t strobe; 

    union
    {
        struct
        {
            uint32_t mosi;                    
            uint32_t miso;                    
            uint32_t spi_reserved[NRFX_MAX(
                                      NRF_SQSPI_MAX_NUM_DATA_LINES - 2,
                                      0)];    
        };
 
        uint32_t
            io[NRF_SQSPI_MAX_NUM_DATA_LINES]; 

        struct
        {
            uint32_t data;                    
            uint32_t one_line_reserved[NRF_SQSPI_MAX_NUM_DATA_LINES -
                                       1];    
        };
    };
} nrf_sqspi_pins_t;
 
#define NRF_SQSPI_PINS_UNUSED \
  UINT32_MAX                        

typedef struct
{
    nrf_sqspi_pins_t pins;          
    bool             skip_gpio_cfg; 
    bool             skip_pmux_cfg; 
 
    uint8_t          irq_priority;  
} nrf_sqspi_cfg_t;

typedef enum
{
    NRF_SQSPI_SAMPLE_SYNC_SCK,    
    NRF_SQSPI_SAMPLE_SYNC_DELAY,  

    NRF_SQSPI_SAMPLE_SYNC_CLK_IN, 

} nrf_sqspi_sample_sync_t;

typedef enum
{
    NRF_SQSPI_SPI_CPOLPHA_0, 
    NRF_SQSPI_SPI_CPOLPHA_1, 
    NRF_SQSPI_SPI_CPOLPHA_2, 
    NRF_SQSPI_SPI_CPOLPHA_3, 
} nrf_sqspi_spi_cpolpha_t;

typedef enum
{
    NRF_SQSPI_PROTO_SPI_C, 
    NRF_SQSPI_PROTO_SPI_T, 
    NRF_SQSPI_PROTO_SSP_C, 
    NRF_SQSPI_PROTO_SSP_T, 
    NRF_SQSPI_PROTO_MW_C,  
    NRF_SQSPI_PROTO_MW_T,  
} nrf_sqspi_proto_t;

typedef enum
{
    NRF_SQSPI_SPI_LINES_SINGLE,      
    NRF_SQSPI_SPI_LINES_DUAL_2_2_2,  
    NRF_SQSPI_SPI_LINES_DUAL_1_1_2,  
    NRF_SQSPI_SPI_LINES_DUAL_1_2_2,  
    NRF_SQSPI_SPI_LINES_QUAD_4_4_4,  
    NRF_SQSPI_SPI_LINES_QUAD_1_1_4,  
    NRF_SQSPI_SPI_LINES_QUAD_1_4_4,  
    NRF_SQSPI_SPI_LINES_OCTAL_8_8_8, 
    NRF_SQSPI_SPI_LINES_OCTAL_1_1_8, 
    NRF_SQSPI_SPI_LINES_OCTAL_1_8_8, 
} nrf_sqspi_spi_lines_t;

typedef enum
{
    NRF_SQSPI_SPI_DDR_SINGLE, 
    NRF_SQSPI_SPI_DDR_S_S_D,  
    NRF_SQSPI_SPI_DDR_S_D_D,  
    NRF_SQSPI_SPI_DDR_DUAL,   
} nrf_sqspi_spi_ddr_t;

typedef enum
{
    NRF_SQSPI_SPI_XIP_MODE_DISABLED,   
    NRF_SQSPI_SPI_XIP_MODE_READ_ONLY,  
    NRF_SQSPI_SPI_XIP_MODE_READ_WRITE, 
} nrf_sqspi_spi_xip_mode_t;

typedef struct
{
    nrf_sqspi_spi_xip_mode_t mode;           
    uint32_t                 address_offset; 

    uint32_t                 size;           
 
    uint32_t                 read_cmd;       
    uint32_t                 write_cmd;      
    uint8_t                  cmd_size;       
    uint8_t                  address_size;   
} nrf_sqspi_spi_xip_cfg_t;

typedef struct
{
    uint32_t          csn_pin;          
    uint32_t          sck_freq_khz;     
    nrf_sqspi_proto_t protocol;         
    nrf_sqspi_sample_sync_t
                      sample_sync;      
    uint16_t          sample_delay_cyc; 


    union
    {
        struct
        {
            nrf_sqspi_spi_cpolpha_t
                                spi_cpolpha;     
            nrf_sqspi_spi_lines_t
                                mspi_lines;      
            nrf_sqspi_spi_ddr_t mspi_ddr;        
            bool                spi_clk_stretch; 

            nrf_sqspi_spi_xip_cfg_t
                                xip_cfg;         
        };

        struct
        {
      /* Intentionally empty: no additional configuration for SSP */
            char ssp_dummy_field; 
        };

        struct
        {
      /* Intentionally empty: no additional configuration for MW */
            char mw_dummy_field; 
        };
    };
} nrf_sqspi_dev_cfg_t;

typedef enum
{
    NRF_SQSPI_XFER_DIR_TXRX, 
    NRF_SQSPI_XFER_DIR_TX,   
    NRF_SQSPI_XFER_DIR_RX,   
} nrf_sqspi_xfer_dir_t;

typedef struct
{
    uint32_t             cmd;          
    uint64_t             address;      
    void *               p_data;       
    size_t               data_length;  
    uint8_t
                         cmd_length;   
    uint8_t              addr_length;  
    uint8_t              dummy_length; 

    nrf_sqspi_xfer_dir_t dir;          
} nrf_sqspi_xfer_t;

#define NRF_SQSPI_FLAG_HOLD_XFER (1UL << 0)

typedef enum
{
    NRF_SQSPI_DATA_FMT_BIT_ORDER_MSB_FIRST, 
    NRF_SQSPI_DATA_FMT_BIT_ORDER_LSB_FIRST, 
} nrf_sqspi_data_fmt_bit_order_t;

typedef enum
{
    NRF_SQSPI_DATA_FMT_PAD_RAW,              
    NRF_SQSPI_DATA_FMT_PAD_MEM_32B_WIRE_8B,  
    NRF_SQSPI_DATA_FMT_PAD_MEM_4B_WIRE_32B,  
    NRF_SQSPI_DATA_FMT_PAD_MEM_8B_WIRE_32B,  
    NRF_SQSPI_DATA_FMT_PAD_MEM_16B_WIRE_32B, 
} nrf_sqspi_data_fmt_pad_t;

typedef struct
{
    nrf_sqspi_data_fmt_bit_order_t cmd_bit_order;         
    nrf_sqspi_data_fmt_bit_order_t addr_bit_order;        
    nrf_sqspi_data_fmt_bit_order_t data_bit_order;        
    uint8_t                        data_bit_reorder_unit; 

 
    uint8_t                        data_container;        

    uint8_t                        data_swap_unit;        

 
    nrf_sqspi_data_fmt_pad_t       data_padding;          
} nrf_sqspi_data_fmt_t;

nrf_sqspi_error_t nrf_sqspi_init(nrf_sqspi_t const *     p_qspi,
                                 nrf_sqspi_cfg_t const * p_config);

bool nrf_sqspi_init_check(nrf_sqspi_t const * p_qspi);

nrf_sqspi_error_t nrf_sqspi_reconfigure(nrf_sqspi_t const *     p_qspi,
                                        nrf_sqspi_cfg_t const * p_config);

void nrf_sqspi_uninit(nrf_sqspi_t const * p_qspi);

nrf_sqspi_error_t nrf_sqspi_dev_cfg(nrf_sqspi_t const *         p_qspi,
                                    nrf_sqspi_dev_cfg_t const * p_config,
                                    nrf_sqspi_callback_t        callback,
                                    void *                      p_context);

nrf_sqspi_error_t nrf_sqspi_dev_data_fmt_set(nrf_sqspi_t const *    p_qspi,
                                             nrf_sqspi_data_fmt_t * p_data_fmt);

nrf_sqspi_error_t nrf_sqspi_activate(nrf_sqspi_t const * p_qspi);

nrf_sqspi_error_t nrf_sqspi_dppi_role_map_set(nrf_sqspi_t const * p_qspi,
                                              const uint8_t *     p_roles);

nrf_sqspi_error_t nrf_sqspi_dppi_subscribe_enable(nrf_sqspi_t const * p_qspi,
                                                  uint8_t             slot,
                                                  bool                enable);

nrf_sqspi_error_t nrf_sqspi_deactivate(nrf_sqspi_t const * p_qspi);

nrf_sqspi_error_t nrf_sqspi_xfer(nrf_sqspi_t const *      p_qspi,
                                 nrf_sqspi_xfer_t const * p_xfer,
                                 size_t                   xfer_count,
                                 uint32_t                 flags);

nrf_sqspi_error_t nrf_sqspi_xfer_prepare(nrf_sqspi_t const *      p_qspi,
                                         nrf_sqspi_xfer_t const * p_xfer,
                                         size_t                   xfer_count);

uint32_t * nrf_sqspi_start_task_address_get(nrf_sqspi_t const * p_qspi);

void nrf_sqspi_irq_handler(void);

 
#ifdef __cplusplus
}
#endif
 
#endif /* NRF_SQSPI_H__ */