doxygen/html/nrf__sp__emmc_8h_source.html

/*

 * Copyright (c) 2025 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

 */


#ifndef NRF_SP_EMMC_H__

#define NRF_SP_EMMC_H__


#ifdef __cplusplus

extern "C" {

#endif


#include "nrfx.h"                                     // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc.

/* ===========================================================================================================================

 * ================                                          SP_EMMC                                          ================

 * ===========================================================================================================================*/


#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)


/* ================================================== Struct SP_EMMC_CONFIG ================================================== */


typedef struct

{

    __IOM uint32_t READYTOTRANSFER;

    __IOM uint32_t CLKFREQHZ;

    __IOM uint32_t BUSWIDTH;

    __IOM uint32_t READDELAY;

    __IOM uint32_t POLLMODE;

    __IOM uint32_t TIMEOUT;

} NRF_SP_EMMC_CONFIG_Type;


/* SP_EMMC_CONFIG_READYTOTRANSFER: Indicates that SEMMC has parsed a configuration and it is ready to transfer */

  #define SP_EMMC_CONFIG_READYTOTRANSFER_ResetValue (0x00000000UL)


/* READYTOTRANSFER @Bit 0 : SEMMC is ready to transfer */

  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos      (0UL)


  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Msk                                                                       \

                                                                     (0x1UL << SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos) \


  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Min      (0x0UL)

  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Max      (0x1UL)

  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_NotReady (0x0UL)

  #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Ready    (0x1UL)


/* SP_EMMC_CONFIG_CLKFREQHZ: SEMMC Clock Frequency in Hz */

  #define SP_EMMC_CONFIG_CLKFREQHZ_ResetValue (0x00000000UL)


/* CLKFREQHZ @Bits 0..31 : SEMMC Clock Frequency in Hz */

  #define SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos (0UL)


  #define SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Msk                                                             \

                                                    (0xFFFFFFFFUL << SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos) \


/* SP_EMMC_CONFIG_BUSWIDTH: SEMMC Bus width */

  #define SP_EMMC_CONFIG_BUSWIDTH_ResetValue (0x00000001UL)


/* BUSWIDTH @Bits 0..3 : Bus width SEMMC will use for data transfers */

  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos        (0UL)


  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Msk                                                           \

                                                         (0xFUL << SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos) \


  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Min        (0x1UL)

  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Max        (0x8UL)

  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_ONELANE    (0x1UL)

  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_FOURLANES  (0x4UL)

  #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_EIGHTLANES (0x8UL)


/* SP_EMMC_CONFIG_READDELAY: Number of FLPR clock cycles to offset for data sampling point */

  #define SP_EMMC_CONFIG_READDELAY_ResetValue (0x00000000UL)


/* READDELAY @Bits 0..31 : Number of FLPR clock cycles to offset for data sampling point */

  #define SP_EMMC_CONFIG_READDELAY_READDELAY_Pos (0UL)


  #define SP_EMMC_CONFIG_READDELAY_READDELAY_Msk                                                             \

                                                    (0xFFFFFFFFUL << SP_EMMC_CONFIG_READDELAY_READDELAY_Pos) \


/* SP_EMMC_CONFIG_POLLMODE: sEMMC DAT0 poll function */

  #define SP_EMMC_CONFIG_POLLMODE_ResetValue (0x00000000UL)


/* POLLMODE @Bit 0 : sEMMC DAT0 poll function */

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_Pos    (0UL)

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_Msk    (0x1UL << SP_EMMC_CONFIG_POLLMODE_POLLMODE_Pos)

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_Min    (0x0UL)

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_Max    (0x1UL)

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_NOPOLL (0x0UL)

  #define SP_EMMC_CONFIG_POLLMODE_POLLMODE_POLL   (0x1UL)


/* SP_EMMC_CONFIG_TIMEOUT: Poll timeout */

  #define SP_EMMC_CONFIG_TIMEOUT_ResetValue (0x00000000UL)


/* TIMEOUT @Bits 0..31 : Number of micro seconds to wait for DAT0 to go high */

  #define SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Pos (0UL)

  #define SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Msk (0xFFFFFFFFUL << SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Pos)


/* ================================================= Struct SP_EMMC_COMMAND ================================================== */


typedef struct

{

    __IOM uint32_t CMD;

    __IOM uint32_t ARG;

    __IOM uint32_t RESPONSEADDR;

    __IOM uint32_t RESPONSE[4];

} NRF_SP_EMMC_COMMAND_Type;


/* SP_EMMC_COMMAND_CMD: Command */

  #define SP_EMMC_COMMAND_CMD_ResetValue (0x00000000UL)


/* IDX @Bits 0..15 : Command index */

  #define SP_EMMC_COMMAND_CMD_IDX_Pos (0UL)

  #define SP_EMMC_COMMAND_CMD_IDX_Msk (0xFFFFUL << SP_EMMC_COMMAND_CMD_IDX_Pos)


/* RESPTYPE @Bits 16..23 : Response type */

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_Pos  (16UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_Msk  (0xFFUL << SP_EMMC_COMMAND_CMD_RESPTYPE_Pos)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_Min  (0x00UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_Max  (0x08UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_NONE (0x00UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R1   (0x01UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R1B  (0x02UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R2   (0x03UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R3   (0x04UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R4   (0x05UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R5   (0x06UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R6   (0x07UL)

  #define SP_EMMC_COMMAND_CMD_RESPTYPE_R7   (0x08UL)


/* RESPPROC @Bits 24..31 : Response process */

  #define SP_EMMC_COMMAND_CMD_RESPPROC_Pos     (24UL)

  #define SP_EMMC_COMMAND_CMD_RESPPROC_Msk     (0xFFUL << SP_EMMC_COMMAND_CMD_RESPPROC_Pos)

  #define SP_EMMC_COMMAND_CMD_RESPPROC_Min     (0x00UL)

  #define SP_EMMC_COMMAND_CMD_RESPPROC_Max     (0x01UL)

  #define SP_EMMC_COMMAND_CMD_RESPPROC_PROCESS (0x00UL)

  #define SP_EMMC_COMMAND_CMD_RESPPROC_IGNORE  (0x01UL)


/* SP_EMMC_COMMAND_ARG: Command argument */

  #define SP_EMMC_COMMAND_ARG_ResetValue (0x00000000UL)


/* ARG @Bits 0..31 : Argument */

  #define SP_EMMC_COMMAND_ARG_ARG_Pos (0UL)

  #define SP_EMMC_COMMAND_ARG_ARG_Msk (0xFFFFFFFFUL << SP_EMMC_COMMAND_ARG_ARG_Pos)


/* SP_EMMC_COMMAND_RESPONSEADDR: Command response buffer address */

  #define SP_EMMC_COMMAND_RESPONSEADDR_ResetValue (0x00000000UL)


/* RESPONSEADDR @Bits 0..31 : Memory address to which SEMMC will copy the response for a command This address is assumed to be

 *                            the beginning of an array of 4 32 bit words. Meant to be used for a pointer in red code */


  #define SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos (0UL)


  #define SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Msk                                                                    \

                                                           (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos) \


/* SP_EMMC_COMMAND_RESPONSE: Command response */

  #define SP_EMMC_COMMAND_RESPONSE_MaxCount   (4UL)

  #define SP_EMMC_COMMAND_RESPONSE_MaxIndex   (3UL)

  #define SP_EMMC_COMMAND_RESPONSE_MinIndex   (0UL)

  #define SP_EMMC_COMMAND_RESPONSE_ResetValue (0x00000000UL)


/* RESPONSE @Bits 0..31 : (unspecified) */

  #define SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos (0UL)


  #define SP_EMMC_COMMAND_RESPONSE_RESPONSE_Msk                                                            \

                                                   (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos) \


/* =================================================== Struct SP_EMMC_DATA =================================================== */


typedef struct

{

    __IOM uint32_t BUFFERADDR;

    __IOM uint32_t BLOCKSIZE;

    __IOM uint32_t BLOCKNUM;

    __IOM uint32_t BLOCKSDONE;

    __IOM uint32_t DIRECTION;

    __IOM uint32_t SKIPDATACRC;

} NRF_SP_EMMC_DATA_Type;


/* SP_EMMC_DATA_BUFFERADDR: Address of the data buffer */

  #define SP_EMMC_DATA_BUFFERADDR_ResetValue (0x00000000UL)


/* BUFFERADDR @Bits 0..31 : Address of the data buffer */

  #define SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos (0UL)


  #define SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Msk                                                             \

                                                    (0xFFFFFFFFUL << SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos) \


/* SP_EMMC_DATA_BLOCKSIZE: Block size */

  #define SP_EMMC_DATA_BLOCKSIZE_ResetValue (0x00000200UL)


/* BLOCKSIZE @Bits 0..31 : Block size */

  #define SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos (0UL)


  #define SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Msk                                                           \

                                                  (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos) \


/* SP_EMMC_DATA_BLOCKNUM: Number of blocks to transfer */

  #define SP_EMMC_DATA_BLOCKNUM_ResetValue (0x00000001UL)


/* BLOCKNUM @Bits 0..31 : Number of blocks */

  #define SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos (0UL)

  #define SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos)


/* SP_EMMC_DATA_BLOCKSDONE: Number of completed blocks */

  #define SP_EMMC_DATA_BLOCKSDONE_ResetValue (0x00000000UL)


/* BLOCKSDONE @Bits 0..31 : Number of completed blocks */

  #define SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Pos (0UL)


  #define SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Msk                                                             \

                                                    (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Pos) \


/* SP_EMMC_DATA_DIRECTION: Direction of data transfer */

  #define SP_EMMC_DATA_DIRECTION_ResetValue (0x00000001UL)


/* DIRECTION @Bit 0 : Direction of data transfer */

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_Pos (0UL)

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_Msk (0x1UL << SP_EMMC_DATA_DIRECTION_DIRECTION_Pos)

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_Min (0x0UL)

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_Max (0x1UL)

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_WR  (0x0UL)

  #define SP_EMMC_DATA_DIRECTION_DIRECTION_RD  (0x1UL)


/* SP_EMMC_DATA_SKIPDATACRC: Skip checking for valid data CRC */

  #define SP_EMMC_DATA_SKIPDATACRC_ResetValue (0x00000000UL)


/* SKIPDATACRC @Bit 0 : Skip checking for valid data CRC */

  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Pos          (0UL)


  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Msk                                                                 \

                                                               (0x1UL << SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Pos) \


  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Min          (0x0UL)

  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Max          (0x1UL)

  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_CHECKDATACRC (0x0UL)

  #define SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_SKIPDATACRC  (0x1UL)


/* ================================================== Struct SP_EMMC_STATUS ================================================== */


typedef struct

{

    __IOM uint32_t STATUS;

} NRF_SP_EMMC_STATUS_Type;


/* SP_EMMC_STATUS_STATUS: SEMMC status register */

  #define SP_EMMC_STATUS_STATUS_ResetValue (0x00000000UL)


/* CMDTIMEOUT @Bit 0 : Command timeout */

  #define SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos (0UL)

  #define SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos)


/* CMDCRCERROR @Bit 1 : CRC Error in the command response */

  #define SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos (1UL)

  #define SP_EMMC_STATUS_STATUS_CMDCRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos)


/* DATACRCERROR @Bit 2 : CRC Error during data transfer (read) */

  #define SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos (2UL)

  #define SP_EMMC_STATUS_STATUS_DATACRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos)


/* PROTOCOLERR @Bit 3 : Protocol error, generic error response */

  #define SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos (3UL)

  #define SP_EMMC_STATUS_STATUS_PROTOCOLERR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos)


/* ================================================== Struct SP_EMMC_SPSYNC ================================================== */


typedef struct

{

    __IOM uint32_t AUX[6];

    __IOM uint32_t DPPIMAP;

} NRF_SP_EMMC_SPSYNC_Type;


/* SP_EMMC_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */

  #define SP_EMMC_SPSYNC_AUX_MaxCount   (6UL)

  #define SP_EMMC_SPSYNC_AUX_MaxIndex   (5UL)

  #define SP_EMMC_SPSYNC_AUX_MinIndex   (0UL)

  #define SP_EMMC_SPSYNC_AUX_ResetValue (0x00000000UL)


/* AUX @Bits 0..31 : Auxiliary register */

  #define SP_EMMC_SPSYNC_AUX_AUX_Pos (0UL)

  #define SP_EMMC_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << SP_EMMC_SPSYNC_AUX_AUX_Pos)


/* SP_EMMC_SPSYNC_DPPIMAP: Task to handler map and DPPI subscription permissions */

  #define SP_EMMC_SPSYNC_DPPIMAP_ResetValue (0x03204015UL)


/* VALID @Bits 0..3 : Marks this register as carrying a map the soft peripheral should apply */

  #define SP_EMMC_SPSYNC_DPPIMAP_VALID_Pos   (0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_VALID_Msk   (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_VALID_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_VALID_Min   (0x5UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_VALID_Max   (0x5UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_VALID_Valid (0x5UL)


/* ROLE0 @Bits 4..7 : Handler invoked by task entry 0 (DPPI channel 0) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Pos    (4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE0_STOP   (0x4UL)


/* ROLE1 @Bits 8..11 : Handler invoked by task entry 1 (DPPI channel 1) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Pos    (8UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE1_STOP   (0x4UL)


/* ROLE2 @Bits 12..15 : Handler invoked by task entry 2 (DPPI channel 2) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Pos    (12UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE2_STOP   (0x4UL)


/* ROLE3 @Bits 16..19 : Handler invoked by task entry 3 (DPPI channel 3) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Pos    (16UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE3_STOP   (0x4UL)


/* ROLE4 @Bits 20..23 : Handler invoked by task entry 4 (no DPPI channel) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Pos    (20UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE4_STOP   (0x4UL)


/* ROLE5 @Bits 24..27 : Handler invoked by task entry 5 (no DPPI channel) */

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Pos    (24UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Msk    (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Pos)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Min    (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Max    (0x4UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_NONE   (0x0UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_DPPI0  (0x1UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_CONFIG (0x2UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_ACTION (0x3UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_ROLE5_STOP   (0x4UL)


/* PERMIT @Bits 28..31 : Per slot permission to subscribe the DPPI channel, bit n for task entry n */

  #define SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Pos (28UL)

  #define SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Pos)


/* ===================================================== Struct SP_EMMC ====================================================== */


typedef struct

{

    __OM uint32_t                  TASKS_START;

    __OM uint32_t                  TASKS_RESET;

    __IOM uint32_t                 SUBSCRIBE_START;

    __IOM uint32_t                 SUBSCRIBE_RESET;

    __IOM uint32_t                 EVENTS_XFERCOMPLETE;

    __IOM uint32_t                 EVENTS_ABORTED;

    __IOM uint32_t                 EVENTS_READYTOTRANSFER;

    __IOM uint32_t                 PUBLISH_XFERCOMPLETE;

    __IOM uint32_t                 PUBLISH_ABORTED;

    __IOM uint32_t                 PUBLISH_READYTOTRANSFER;

    __IOM uint32_t                 INTEN;

    __IOM uint32_t                 ENABLE;

    __IOM NRF_SP_EMMC_CONFIG_Type  CONFIG;

    __IOM NRF_SP_EMMC_COMMAND_Type COMMAND;

    __IOM NRF_SP_EMMC_DATA_Type    DATA;

    __IOM NRF_SP_EMMC_STATUS_Type  STATUS;

    __IOM NRF_SP_EMMC_SPSYNC_Type  SPSYNC;

} NRF_SP_EMMC_Type;


/* SP_EMMC_TASKS_START: Trigger this task to send a command (which starts a data transfer, if applicable) */

  #define SP_EMMC_TASKS_START_ResetValue (0x00000000UL)


/* TASKS_START @Bit 0 : Trigger this task to send a command (which starts a data transfer, if applicable) */

  #define SP_EMMC_TASKS_START_TASKS_START_Pos     (0UL)

  #define SP_EMMC_TASKS_START_TASKS_START_Msk     (0x1UL << SP_EMMC_TASKS_START_TASKS_START_Pos)

  #define SP_EMMC_TASKS_START_TASKS_START_Min     (0x1UL)

  #define SP_EMMC_TASKS_START_TASKS_START_Max     (0x1UL)

  #define SP_EMMC_TASKS_START_TASKS_START_Trigger (0x1UL)


/* SP_EMMC_TASKS_RESET: Trigger this task to reset SEMMC to UNINITIALIZED state */

  #define SP_EMMC_TASKS_RESET_ResetValue (0x00000000UL)


/* TASKS_RESET @Bit 0 : Trigger this task to reset SEMMC to UNINITIALIZED state */

  #define SP_EMMC_TASKS_RESET_TASKS_RESET_Pos     (0UL)

  #define SP_EMMC_TASKS_RESET_TASKS_RESET_Msk     (0x1UL << SP_EMMC_TASKS_RESET_TASKS_RESET_Pos)

  #define SP_EMMC_TASKS_RESET_TASKS_RESET_Min     (0x1UL)

  #define SP_EMMC_TASKS_RESET_TASKS_RESET_Max     (0x1UL)

  #define SP_EMMC_TASKS_RESET_TASKS_RESET_Trigger (0x1UL)


/* SP_EMMC_SUBSCRIBE_START: Subscribe configuration for task START */

  #define SP_EMMC_SUBSCRIBE_START_ResetValue (0x00000000UL)


/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */

  #define SP_EMMC_SUBSCRIBE_START_CHIDX_Pos (0UL)

  #define SP_EMMC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_START_CHIDX_Pos)

  #define SP_EMMC_SUBSCRIBE_START_CHIDX_Min (0x00UL)

  #define SP_EMMC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)


/* EN @Bit 31 : (unspecified) */

  #define SP_EMMC_SUBSCRIBE_START_EN_Pos      (31UL)

  #define SP_EMMC_SUBSCRIBE_START_EN_Msk      (0x1UL << SP_EMMC_SUBSCRIBE_START_EN_Pos)

  #define SP_EMMC_SUBSCRIBE_START_EN_Min      (0x0UL)

  #define SP_EMMC_SUBSCRIBE_START_EN_Max      (0x1UL)

  #define SP_EMMC_SUBSCRIBE_START_EN_Disabled (0x0UL)

  #define SP_EMMC_SUBSCRIBE_START_EN_Enabled  (0x1UL)


/* SP_EMMC_SUBSCRIBE_RESET: Subscribe configuration for task RESET */

  #define SP_EMMC_SUBSCRIBE_RESET_ResetValue (0x00000000UL)


/* CHIDX @Bits 0..7 : DPPI channel that task RESET will subscribe to */

  #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos (0UL)

  #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos)

  #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Min (0x00UL)

  #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL)


/* EN @Bit 31 : (unspecified) */

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Pos      (31UL)

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Msk      (0x1UL << SP_EMMC_SUBSCRIBE_RESET_EN_Pos)

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Min      (0x0UL)

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Max      (0x1UL)

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Disabled (0x0UL)

  #define SP_EMMC_SUBSCRIBE_RESET_EN_Enabled  (0x1UL)


/* SP_EMMC_EVENTS_XFERCOMPLETE: This event signals that SEMMC has completed a command or transfer (if applicable) */

  #define SP_EMMC_EVENTS_XFERCOMPLETE_ResetValue (0x00000000UL)


/* EVENTS_XFERCOMPLETE @Bit 0 : This event signals that SEMMC has completed a command or transfer (if applicable) */

  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos (0UL)


  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Msk \

                                                                          (0x1UL << SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos)


  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Min          (0x0UL)

  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Max          (0x1UL)

  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_NotGenerated (0x0UL)

  #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Generated    (0x1UL)


/* SP_EMMC_EVENTS_ABORTED: This event signals that SEMMC has aborted in the middle of a command/transfer or has timed out */

  #define SP_EMMC_EVENTS_ABORTED_ResetValue (0x00000000UL)


/* EVENTS_ABORTED @Bit 0 : This event signals that SEMMC has aborted in the middle of a command/transfer or has timed out */

  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos          (0UL)


  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Msk                                                                  \

                                                                (0x1UL << SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos) \


  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Min          (0x0UL)

  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Max          (0x1UL)

  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_NotGenerated (0x0UL)

  #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Generated    (0x1UL)


/* SP_EMMC_EVENTS_READYTOTRANSFER: This event signals that SEMMC is ready to start a transfer */

  #define SP_EMMC_EVENTS_READYTOTRANSFER_ResetValue (0x00000000UL)


/* EVENTS_READYTOTRANSFER @Bit 0 : This event signals that SEMMC is ready to start a transfer */

  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos (0UL)


  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Msk \

                                                                                (0x1UL << SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos)


  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Min          (0x0UL)

  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Max          (0x1UL)

  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_NotGenerated (0x0UL)

  #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Generated    (0x1UL)


/* SP_EMMC_PUBLISH_XFERCOMPLETE: Publish configuration for event XFERCOMPLETE */

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_ResetValue (0x00000000UL)


/* CHIDX @Bits 0..7 : DPPI channel that event XFERCOMPLETE will publish to */

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos (0UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Min (0x00UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Max (0xFFUL)


/* EN @Bit 31 : (unspecified) */

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos      (31UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Msk      (0x1UL << SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Min      (0x0UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Max      (0x1UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Disabled (0x0UL)

  #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Enabled  (0x1UL)


/* SP_EMMC_PUBLISH_ABORTED: Publish configuration for event ABORTED */

  #define SP_EMMC_PUBLISH_ABORTED_ResetValue (0x00000000UL)


/* CHIDX @Bits 0..7 : DPPI channel that event ABORTED will publish to */

  #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos (0UL)

  #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos)

  #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Min (0x00UL)

  #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Max (0xFFUL)


/* EN @Bit 31 : (unspecified) */

  #define SP_EMMC_PUBLISH_ABORTED_EN_Pos      (31UL)

  #define SP_EMMC_PUBLISH_ABORTED_EN_Msk      (0x1UL << SP_EMMC_PUBLISH_ABORTED_EN_Pos)

  #define SP_EMMC_PUBLISH_ABORTED_EN_Min      (0x0UL)

  #define SP_EMMC_PUBLISH_ABORTED_EN_Max      (0x1UL)

  #define SP_EMMC_PUBLISH_ABORTED_EN_Disabled (0x0UL)

  #define SP_EMMC_PUBLISH_ABORTED_EN_Enabled  (0x1UL)


/* SP_EMMC_PUBLISH_READYTOTRANSFER: Publish configuration for event READYTOTRANSFER */

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_ResetValue (0x00000000UL)


/* CHIDX @Bits 0..7 : DPPI channel that event READYTOTRANSFER will publish to */

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Pos (0UL)


  #define SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Msk                                                          \

                                                       (0xFFUL << SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Pos) \


  #define SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Min (0x00UL)

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Max (0xFFUL)


/* EN @Bit 31 : (unspecified) */

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Pos      (31UL)


  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Msk                                                           \

                                                         (0x1UL << SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Pos) \


  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Min      (0x0UL)

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Max      (0x1UL)

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Disabled (0x0UL)

  #define SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Enabled  (0x1UL)


/* SP_EMMC_INTEN: Enable or disable interrupt */

  #define SP_EMMC_INTEN_ResetValue (0x00000000UL)


/* XFERCOMPLETE @Bit 0 : Enable or disable interrupt for event XFERCOMPLETE */

  #define SP_EMMC_INTEN_XFERCOMPLETE_Pos      (0UL)

  #define SP_EMMC_INTEN_XFERCOMPLETE_Msk      (0x1UL << SP_EMMC_INTEN_XFERCOMPLETE_Pos)

  #define SP_EMMC_INTEN_XFERCOMPLETE_Min      (0x0UL)

  #define SP_EMMC_INTEN_XFERCOMPLETE_Max      (0x1UL)

  #define SP_EMMC_INTEN_XFERCOMPLETE_Disabled (0x0UL)

  #define SP_EMMC_INTEN_XFERCOMPLETE_Enabled  (0x1UL)


/* ABORTED @Bit 1 : Enable or disable interrupt for event ABORTED */

  #define SP_EMMC_INTEN_ABORTED_Pos      (1UL)

  #define SP_EMMC_INTEN_ABORTED_Msk      (0x1UL << SP_EMMC_INTEN_ABORTED_Pos)

  #define SP_EMMC_INTEN_ABORTED_Min      (0x0UL)

  #define SP_EMMC_INTEN_ABORTED_Max      (0x1UL)

  #define SP_EMMC_INTEN_ABORTED_Disabled (0x0UL)

  #define SP_EMMC_INTEN_ABORTED_Enabled  (0x1UL)


/* READYTOTRANSFER @Bit 2 : Enable or disable interrupt for event READYTOTRANSFER */

  #define SP_EMMC_INTEN_READYTOTRANSFER_Pos      (2UL)

  #define SP_EMMC_INTEN_READYTOTRANSFER_Msk      (0x1UL << SP_EMMC_INTEN_READYTOTRANSFER_Pos)

  #define SP_EMMC_INTEN_READYTOTRANSFER_Min      (0x0UL)

  #define SP_EMMC_INTEN_READYTOTRANSFER_Max      (0x1UL)

  #define SP_EMMC_INTEN_READYTOTRANSFER_Disabled (0x0UL)

  #define SP_EMMC_INTEN_READYTOTRANSFER_Enabled  (0x1UL)


/* SP_EMMC_ENABLE: Enable the SEMMC peripheral */

  #define SP_EMMC_ENABLE_ResetValue (0x00000000UL)


/* ENABLE @Bit 0 : Enable or disable SEMMC */

  #define SP_EMMC_ENABLE_ENABLE_Pos      (0UL)

  #define SP_EMMC_ENABLE_ENABLE_Msk      (0x1UL << SP_EMMC_ENABLE_ENABLE_Pos)

  #define SP_EMMC_ENABLE_ENABLE_Min      (0x0UL)

  #define SP_EMMC_ENABLE_ENABLE_Max      (0x1UL)

  #define SP_EMMC_ENABLE_ENABLE_Disabled (0x0UL)

  #define SP_EMMC_ENABLE_ENABLE_Enabled  (0x1UL)


#endif \


#endif /* NRF_SP_EMMC_H__ */

NRF_SP_EMMC_COMMAND_Type::RESPONSEADDR
__IOM uint32_t RESPONSEADDR
Definition nrf_sp_emmc.h:112

NRF_SP_EMMC_COMMAND_Type::RESPONSE
__IOM uint32_t RESPONSE[4]
Definition nrf_sp_emmc.h:113

NRF_SP_EMMC_COMMAND_Type::CMD
__IOM uint32_t CMD
Definition nrf_sp_emmc.h:110

NRF_SP_EMMC_COMMAND_Type::ARG
__IOM uint32_t ARG
Definition nrf_sp_emmc.h:111

NRF_SP_EMMC_COMMAND_Type
COMMAND [SP_EMMC_COMMAND] SEMMC command descriptor.
Definition nrf_sp_emmc.h:109

NRF_SP_EMMC_CONFIG_Type::TIMEOUT
__IOM uint32_t TIMEOUT
Definition nrf_sp_emmc.h:34

NRF_SP_EMMC_CONFIG_Type::POLLMODE
__IOM uint32_t POLLMODE
Definition nrf_sp_emmc.h:33

NRF_SP_EMMC_CONFIG_Type::CLKFREQHZ
__IOM uint32_t CLKFREQHZ
Definition nrf_sp_emmc.h:29

NRF_SP_EMMC_CONFIG_Type::READDELAY
__IOM uint32_t READDELAY
Definition nrf_sp_emmc.h:31

NRF_SP_EMMC_CONFIG_Type::READYTOTRANSFER
__IOM uint32_t READYTOTRANSFER
Definition nrf_sp_emmc.h:27

NRF_SP_EMMC_CONFIG_Type::BUSWIDTH
__IOM uint32_t BUSWIDTH
Definition nrf_sp_emmc.h:30

NRF_SP_EMMC_CONFIG_Type
CONFIG [SP_EMMC_CONFIG] SEMMC configuration.
Definition nrf_sp_emmc.h:26

NRF_SP_EMMC_DATA_Type::DIRECTION
__IOM uint32_t DIRECTION
Definition nrf_sp_emmc.h:188

NRF_SP_EMMC_DATA_Type::SKIPDATACRC
__IOM uint32_t SKIPDATACRC
Definition nrf_sp_emmc.h:189

NRF_SP_EMMC_DATA_Type::BUFFERADDR
__IOM uint32_t BUFFERADDR
Definition nrf_sp_emmc.h:184

NRF_SP_EMMC_DATA_Type::BLOCKSDONE
__IOM uint32_t BLOCKSDONE
Definition nrf_sp_emmc.h:187

NRF_SP_EMMC_DATA_Type::BLOCKSIZE
__IOM uint32_t BLOCKSIZE
Definition nrf_sp_emmc.h:185

NRF_SP_EMMC_DATA_Type::BLOCKNUM
__IOM uint32_t BLOCKNUM
Definition nrf_sp_emmc.h:186

NRF_SP_EMMC_DATA_Type
DATA [SP_EMMC_DATA] SEMMC data transfer descriptor.
Definition nrf_sp_emmc.h:183

NRF_SP_EMMC_SPSYNC_Type::DPPIMAP
__IOM uint32_t DPPIMAP
Definition nrf_sp_emmc.h:295

NRF_SP_EMMC_SPSYNC_Type::AUX
__IOM uint32_t AUX[6]
Definition nrf_sp_emmc.h:294

NRF_SP_EMMC_SPSYNC_Type
SPSYNC [SP_EMMC_SPSYNC] Registers used to acknowledge API function calls.
Definition nrf_sp_emmc.h:293

NRF_SP_EMMC_STATUS_Type::STATUS
__IOM uint32_t STATUS
Definition nrf_sp_emmc.h:262

NRF_SP_EMMC_STATUS_Type
STATUS [SP_EMMC_STATUS] SEMMC status.
Definition nrf_sp_emmc.h:261

NRF_SP_EMMC_Type::TASKS_START
__OM uint32_t TASKS_START
Definition nrf_sp_emmc.h:412

NRF_SP_EMMC_Type::STATUS
__IOM NRF_SP_EMMC_STATUS_Type STATUS
Definition nrf_sp_emmc.h:432

NRF_SP_EMMC_Type::EVENTS_READYTOTRANSFER
__IOM uint32_t EVENTS_READYTOTRANSFER
Definition nrf_sp_emmc.h:422

NRF_SP_EMMC_Type::TASKS_RESET
__OM uint32_t TASKS_RESET
Definition nrf_sp_emmc.h:414

NRF_SP_EMMC_Type::PUBLISH_XFERCOMPLETE
__IOM uint32_t PUBLISH_XFERCOMPLETE
Definition nrf_sp_emmc.h:424

NRF_SP_EMMC_Type::COMMAND
__IOM NRF_SP_EMMC_COMMAND_Type COMMAND
Definition nrf_sp_emmc.h:430

NRF_SP_EMMC_Type::EVENTS_ABORTED
__IOM uint32_t EVENTS_ABORTED
Definition nrf_sp_emmc.h:420

NRF_SP_EMMC_Type::EVENTS_XFERCOMPLETE
__IOM uint32_t EVENTS_XFERCOMPLETE
Definition nrf_sp_emmc.h:418

NRF_SP_EMMC_Type::ENABLE
__IOM uint32_t ENABLE
Definition nrf_sp_emmc.h:428

NRF_SP_EMMC_Type::PUBLISH_ABORTED
__IOM uint32_t PUBLISH_ABORTED
Definition nrf_sp_emmc.h:425

NRF_SP_EMMC_Type::PUBLISH_READYTOTRANSFER
__IOM uint32_t PUBLISH_READYTOTRANSFER
Definition nrf_sp_emmc.h:426

NRF_SP_EMMC_Type::SPSYNC
__IOM NRF_SP_EMMC_SPSYNC_Type SPSYNC
Definition nrf_sp_emmc.h:433

NRF_SP_EMMC_Type::DATA
__IOM NRF_SP_EMMC_DATA_Type DATA
Definition nrf_sp_emmc.h:431

NRF_SP_EMMC_Type::SUBSCRIBE_START
__IOM uint32_t SUBSCRIBE_START
Definition nrf_sp_emmc.h:416

NRF_SP_EMMC_Type::CONFIG
__IOM NRF_SP_EMMC_CONFIG_Type CONFIG
Definition nrf_sp_emmc.h:429

NRF_SP_EMMC_Type::SUBSCRIBE_RESET
__IOM uint32_t SUBSCRIBE_RESET
Definition nrf_sp_emmc.h:417

NRF_SP_EMMC_Type::INTEN
__IOM uint32_t INTEN
Definition nrf_sp_emmc.h:427

NRF_SP_EMMC_Type
Soft peripheral eMMC.
Definition nrf_sp_emmc.h:411