#include "nrfx.h"

Go to the source code of this file.

Data Structures
struct	NRF_SP_EMMC_CONFIG_Type
	CONFIG [SP_EMMC_CONFIG] SEMMC configuration. More...
struct	NRF_SP_EMMC_COMMAND_Type
	COMMAND [SP_EMMC_COMMAND] SEMMC command descriptor. More...
struct	NRF_SP_EMMC_DATA_Type
	DATA [SP_EMMC_DATA] SEMMC data transfer descriptor. More...
struct	NRF_SP_EMMC_STATUS_Type
	STATUS [SP_EMMC_STATUS] SEMMC status. More...
struct	NRF_SP_EMMC_SPSYNC_Type
	SPSYNC [SP_EMMC_SPSYNC] Registers used to acknowledge API function calls. More...
struct	NRF_SP_EMMC_Type
	Soft peripheral eMMC. More...

Macros
#define	SP_EMMC_CONFIG_READYTOTRANSFER_ResetValue (0x00000000UL)
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos (0UL)
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Msk (0x1UL << SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos) \
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Min (0x0UL)
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Max (0x1UL)
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_NotReady (0x0UL)
#define	SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Ready (0x1UL)
#define	SP_EMMC_CONFIG_CLKFREQHZ_ResetValue (0x00000000UL)
#define	SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos (0UL)
#define	SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Msk (0xFFFFFFFFUL << SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos) \
#define	SP_EMMC_CONFIG_BUSWIDTH_ResetValue (0x00000001UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos (0UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Msk (0xFUL << SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos) \
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Min (0x1UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Max (0x8UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_ONELANE (0x1UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_FOURLANES (0x4UL)
#define	SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_EIGHTLANES (0x8UL)
#define	SP_EMMC_CONFIG_READDELAY_ResetValue (0x00000000UL)
#define	SP_EMMC_CONFIG_READDELAY_READDELAY_Pos (0UL)
#define	SP_EMMC_CONFIG_READDELAY_READDELAY_Msk (0xFFFFFFFFUL << SP_EMMC_CONFIG_READDELAY_READDELAY_Pos) \
#define	SP_EMMC_CONFIG_POLLMODE_ResetValue (0x00000000UL)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_Pos (0UL)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_Msk (0x1UL << SP_EMMC_CONFIG_POLLMODE_POLLMODE_Pos)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_Min (0x0UL)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_Max (0x1UL)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_NOPOLL (0x0UL)
#define	SP_EMMC_CONFIG_POLLMODE_POLLMODE_POLL (0x1UL)
#define	SP_EMMC_CONFIG_TIMEOUT_ResetValue (0x00000000UL)
#define	SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Pos (0UL)
#define	SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Msk (0xFFFFFFFFUL << SP_EMMC_CONFIG_TIMEOUT_TIMEOUT_Pos)
#define	SP_EMMC_COMMAND_CMD_ResetValue (0x00000000UL)
#define	SP_EMMC_COMMAND_CMD_IDX_Pos (0UL)
#define	SP_EMMC_COMMAND_CMD_IDX_Msk (0xFFFFUL << SP_EMMC_COMMAND_CMD_IDX_Pos)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_Pos (16UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_Msk (0xFFUL << SP_EMMC_COMMAND_CMD_RESPTYPE_Pos)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_Min (0x00UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_Max (0x08UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_NONE (0x00UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R1 (0x01UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R1B (0x02UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R2 (0x03UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R3 (0x04UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R4 (0x05UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R5 (0x06UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R6 (0x07UL)
#define	SP_EMMC_COMMAND_CMD_RESPTYPE_R7 (0x08UL)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_Pos (24UL)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_Msk (0xFFUL << SP_EMMC_COMMAND_CMD_RESPPROC_Pos)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_Min (0x00UL)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_Max (0x01UL)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_PROCESS (0x00UL)
#define	SP_EMMC_COMMAND_CMD_RESPPROC_IGNORE (0x01UL)
#define	SP_EMMC_COMMAND_ARG_ResetValue (0x00000000UL)
#define	SP_EMMC_COMMAND_ARG_ARG_Pos (0UL)
#define	SP_EMMC_COMMAND_ARG_ARG_Msk (0xFFFFFFFFUL << SP_EMMC_COMMAND_ARG_ARG_Pos)
#define	SP_EMMC_COMMAND_RESPONSEADDR_ResetValue (0x00000000UL)
#define	SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos (0UL)
#define	SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Msk (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos) \
#define	SP_EMMC_COMMAND_RESPONSE_MaxCount (4UL)
#define	SP_EMMC_COMMAND_RESPONSE_MaxIndex (3UL)
#define	SP_EMMC_COMMAND_RESPONSE_MinIndex (0UL)
#define	SP_EMMC_COMMAND_RESPONSE_ResetValue (0x00000000UL)
#define	SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos (0UL)
#define	SP_EMMC_COMMAND_RESPONSE_RESPONSE_Msk (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos) \
#define	SP_EMMC_DATA_BUFFERADDR_ResetValue (0x00000000UL)
#define	SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos (0UL)
#define	SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos) \
#define	SP_EMMC_DATA_BLOCKSIZE_ResetValue (0x00000200UL)
#define	SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos (0UL)
#define	SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos) \
#define	SP_EMMC_DATA_BLOCKNUM_ResetValue (0x00000001UL)
#define	SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos (0UL)
#define	SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos)
#define	SP_EMMC_DATA_BLOCKSDONE_ResetValue (0x00000000UL)
#define	SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Pos (0UL)
#define	SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKSDONE_BLOCKSDONE_Pos) \
#define	SP_EMMC_DATA_DIRECTION_ResetValue (0x00000001UL)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_Pos (0UL)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_Msk (0x1UL << SP_EMMC_DATA_DIRECTION_DIRECTION_Pos)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_Min (0x0UL)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_Max (0x1UL)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_WR (0x0UL)
#define	SP_EMMC_DATA_DIRECTION_DIRECTION_RD (0x1UL)
#define	SP_EMMC_DATA_SKIPDATACRC_ResetValue (0x00000000UL)
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Pos (0UL)
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Msk (0x1UL << SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Pos) \
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Min (0x0UL)
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_Max (0x1UL)
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_CHECKDATACRC (0x0UL)
#define	SP_EMMC_DATA_SKIPDATACRC_SKIPDATACRC_SKIPDATACRC (0x1UL)
#define	SP_EMMC_STATUS_STATUS_ResetValue (0x00000000UL)
#define	SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos (0UL)
#define	SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos)
#define	SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos (1UL)
#define	SP_EMMC_STATUS_STATUS_CMDCRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos)
#define	SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos (2UL)
#define	SP_EMMC_STATUS_STATUS_DATACRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos)
#define	SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos (3UL)
#define	SP_EMMC_STATUS_STATUS_PROTOCOLERR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos)
#define	SP_EMMC_SPSYNC_AUX_MaxCount (6UL)
#define	SP_EMMC_SPSYNC_AUX_MaxIndex (5UL)
#define	SP_EMMC_SPSYNC_AUX_MinIndex (0UL)
#define	SP_EMMC_SPSYNC_AUX_ResetValue (0x00000000UL)
#define	SP_EMMC_SPSYNC_AUX_AUX_Pos (0UL)
#define	SP_EMMC_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << SP_EMMC_SPSYNC_AUX_AUX_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ResetValue (0x03204015UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_VALID_Pos (0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_VALID_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_VALID_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_VALID_Min (0x5UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_VALID_Max (0x5UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_VALID_Valid (0x5UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Pos (4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE0_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Pos (8UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE1_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Pos (12UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE2_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Pos (16UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE3_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Pos (20UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE4_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Pos (24UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Pos)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Min (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_Max (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_NONE (0x0UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_DPPI0 (0x1UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_CONFIG (0x2UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_ACTION (0x3UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_ROLE5_STOP (0x4UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Pos (28UL)
#define	SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Msk (0xFUL << SP_EMMC_SPSYNC_DPPIMAP_PERMIT_Pos)
#define	SP_EMMC_TASKS_START_ResetValue (0x00000000UL)
#define	SP_EMMC_TASKS_START_TASKS_START_Pos (0UL)
#define	SP_EMMC_TASKS_START_TASKS_START_Msk (0x1UL << SP_EMMC_TASKS_START_TASKS_START_Pos)
#define	SP_EMMC_TASKS_START_TASKS_START_Min (0x1UL)
#define	SP_EMMC_TASKS_START_TASKS_START_Max (0x1UL)
#define	SP_EMMC_TASKS_START_TASKS_START_Trigger (0x1UL)
#define	SP_EMMC_TASKS_RESET_ResetValue (0x00000000UL)
#define	SP_EMMC_TASKS_RESET_TASKS_RESET_Pos (0UL)
#define	SP_EMMC_TASKS_RESET_TASKS_RESET_Msk (0x1UL << SP_EMMC_TASKS_RESET_TASKS_RESET_Pos)
#define	SP_EMMC_TASKS_RESET_TASKS_RESET_Min (0x1UL)
#define	SP_EMMC_TASKS_RESET_TASKS_RESET_Max (0x1UL)
#define	SP_EMMC_TASKS_RESET_TASKS_RESET_Trigger (0x1UL)
#define	SP_EMMC_SUBSCRIBE_START_ResetValue (0x00000000UL)
#define	SP_EMMC_SUBSCRIBE_START_CHIDX_Pos (0UL)
#define	SP_EMMC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_START_CHIDX_Pos)
#define	SP_EMMC_SUBSCRIBE_START_CHIDX_Min (0x00UL)
#define	SP_EMMC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)
#define	SP_EMMC_SUBSCRIBE_START_EN_Pos (31UL)
#define	SP_EMMC_SUBSCRIBE_START_EN_Msk (0x1UL << SP_EMMC_SUBSCRIBE_START_EN_Pos)
#define	SP_EMMC_SUBSCRIBE_START_EN_Min (0x0UL)
#define	SP_EMMC_SUBSCRIBE_START_EN_Max (0x1UL)
#define	SP_EMMC_SUBSCRIBE_START_EN_Disabled (0x0UL)
#define	SP_EMMC_SUBSCRIBE_START_EN_Enabled (0x1UL)
#define	SP_EMMC_SUBSCRIBE_RESET_ResetValue (0x00000000UL)
#define	SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos (0UL)
#define	SP_EMMC_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos)
#define	SP_EMMC_SUBSCRIBE_RESET_CHIDX_Min (0x00UL)
#define	SP_EMMC_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Pos (31UL)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Msk (0x1UL << SP_EMMC_SUBSCRIBE_RESET_EN_Pos)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Min (0x0UL)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Max (0x1UL)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Disabled (0x0UL)
#define	SP_EMMC_SUBSCRIBE_RESET_EN_Enabled (0x1UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_ResetValue (0x00000000UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos (0UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Msk (0x1UL << SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Min (0x0UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Max (0x1UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_NotGenerated (0x0UL)
#define	SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Generated (0x1UL)
#define	SP_EMMC_EVENTS_ABORTED_ResetValue (0x00000000UL)
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos (0UL)
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Msk (0x1UL << SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos) \
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Min (0x0UL)
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Max (0x1UL)
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_NotGenerated (0x0UL)
#define	SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Generated (0x1UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_ResetValue (0x00000000UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos (0UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Msk (0x1UL << SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Min (0x0UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Max (0x1UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_NotGenerated (0x0UL)
#define	SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Generated (0x1UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_ResetValue (0x00000000UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos (0UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Min (0x00UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Max (0xFFUL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos (31UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Msk (0x1UL << SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Min (0x0UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Max (0x1UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Disabled (0x0UL)
#define	SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Enabled (0x1UL)
#define	SP_EMMC_PUBLISH_ABORTED_ResetValue (0x00000000UL)
#define	SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos (0UL)
#define	SP_EMMC_PUBLISH_ABORTED_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos)
#define	SP_EMMC_PUBLISH_ABORTED_CHIDX_Min (0x00UL)
#define	SP_EMMC_PUBLISH_ABORTED_CHIDX_Max (0xFFUL)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Pos (31UL)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Msk (0x1UL << SP_EMMC_PUBLISH_ABORTED_EN_Pos)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Min (0x0UL)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Max (0x1UL)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Disabled (0x0UL)
#define	SP_EMMC_PUBLISH_ABORTED_EN_Enabled (0x1UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_ResetValue (0x00000000UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Pos (0UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Pos) \
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Min (0x00UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_CHIDX_Max (0xFFUL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Pos (31UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Msk (0x1UL << SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Pos) \
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Min (0x0UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Max (0x1UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Disabled (0x0UL)
#define	SP_EMMC_PUBLISH_READYTOTRANSFER_EN_Enabled (0x1UL)
#define	SP_EMMC_INTEN_ResetValue (0x00000000UL)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Pos (0UL)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Msk (0x1UL << SP_EMMC_INTEN_XFERCOMPLETE_Pos)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Min (0x0UL)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Max (0x1UL)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Disabled (0x0UL)
#define	SP_EMMC_INTEN_XFERCOMPLETE_Enabled (0x1UL)
#define	SP_EMMC_INTEN_ABORTED_Pos (1UL)
#define	SP_EMMC_INTEN_ABORTED_Msk (0x1UL << SP_EMMC_INTEN_ABORTED_Pos)
#define	SP_EMMC_INTEN_ABORTED_Min (0x0UL)
#define	SP_EMMC_INTEN_ABORTED_Max (0x1UL)
#define	SP_EMMC_INTEN_ABORTED_Disabled (0x0UL)
#define	SP_EMMC_INTEN_ABORTED_Enabled (0x1UL)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Pos (2UL)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Msk (0x1UL << SP_EMMC_INTEN_READYTOTRANSFER_Pos)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Min (0x0UL)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Max (0x1UL)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Disabled (0x0UL)
#define	SP_EMMC_INTEN_READYTOTRANSFER_Enabled (0x1UL)
#define	SP_EMMC_ENABLE_ResetValue (0x00000000UL)
#define	SP_EMMC_ENABLE_ENABLE_Pos (0UL)
#define	SP_EMMC_ENABLE_ENABLE_Msk (0x1UL << SP_EMMC_ENABLE_ENABLE_Pos)
#define	SP_EMMC_ENABLE_ENABLE_Min (0x0UL)
#define	SP_EMMC_ENABLE_ENABLE_Max (0x1UL)
#define	SP_EMMC_ENABLE_ENABLE_Disabled (0x0UL)
#define	SP_EMMC_ENABLE_ENABLE_Enabled (0x1UL)

Data Structures

Macros