QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Msk

#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Msk    (0x3UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Pos)

Bit mask of RSVDCTRLR02021 field.