#include "nrfx.h"

Go to the source code of this file.

Data Structures
struct	NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type
	EVENTS_DONE [QSPI_EVENTS_DMA_EVENTS_DONE] Peripheral events. More...

struct	NRF_QSPI_EVENTS_DMA_Type
	EVENTS_DMA [QSPI_EVENTS_DMA] Peripheral events. More...

struct	NRF_QSPI_CONFIG_Type
	CONFIG [QSPI_CONFIG] (unspecified) More...

struct	NRF_QSPI_FORMAT_Type
	FORMAT [QSPI_FORMAT] (unspecified) More...

struct	NRF_QSPI_DMA_STATUS_Type
	STATUS [QSPI_DMA_STATUS] EasyVDMA status registers. More...

struct	NRF_QSPI_DMA_CONFIG_Type
	CONFIG [QSPI_DMA_CONFIG] General config registers. More...

struct	NRF_QSPI_DMA_Type
	DMA [QSPI_DMA] (unspecified) More...

struct	NRF_QSPI_CORE_CORE_Type
	CORE [QSPI_CORE_CORE] (unspecified) More...

struct	NRF_QSPI_CORE_Type
	CORE [QSPI_CORE] (unspecified) More...

struct	NRF_QSPI_SPSYNC_Type
	SPSYNC [QSPI_SPSYNC] Registers used to acknowledge API function calls. More...

struct	NRF_SP_QSPI_Type
	Quad serial peripheral interface. More...

Macros
#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Pos (0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Msk (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Pos)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Min (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Max (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Pos (0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Msk (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Pos)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Min (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Max (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Pos (0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Msk (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Pos)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Min (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Max (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Pos (0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Msk (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Pos)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Min (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Max (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Pos (0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Msk (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Pos)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Min (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Max (0x1UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_ERROR_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_Pos (0UL)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_Msk (0x1UL << QSPI_EVENTS_DMA_ERROR_ERROR_Pos)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_Min (0x0UL)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_Max (0x1UL)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_ERROR_ERROR_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_PAUSED_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_Pos (0UL)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_Msk (0x1UL << QSPI_EVENTS_DMA_PAUSED_PAUSED_Pos)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_Min (0x0UL)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_Max (0x1UL)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_PAUSED_PAUSED_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_RESET_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_RESET_RESET_Pos (0UL)

#define	QSPI_EVENTS_DMA_RESET_RESET_Msk (0x1UL << QSPI_EVENTS_DMA_RESET_RESET_Pos)

#define	QSPI_EVENTS_DMA_RESET_RESET_Min (0x0UL)

#define	QSPI_EVENTS_DMA_RESET_RESET_Max (0x1UL)

#define	QSPI_EVENTS_DMA_RESET_RESET_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_RESET_RESET_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_DONE_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_DONE_DONE_Pos (0UL)

#define	QSPI_EVENTS_DMA_DONE_DONE_Msk (0x1UL << QSPI_EVENTS_DMA_DONE_DONE_Pos)

#define	QSPI_EVENTS_DMA_DONE_DONE_Min (0x0UL)

#define	QSPI_EVENTS_DMA_DONE_DONE_Max (0x1UL)

#define	QSPI_EVENTS_DMA_DONE_DONE_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_DONE_DONE_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Pos (0UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Pos)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Pos (0UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Msk (0x1UL << QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Pos)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Min (0x0UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Max (0x1UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Generated (0x1UL)

#define	QSPI_EVENTS_DMA_ABORTED_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_Pos (0UL)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_Msk (0x1UL << QSPI_EVENTS_DMA_ABORTED_ABORTED_Pos)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_Min (0x0UL)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_Max (0x1UL)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_NotGenerated (0x0UL)

#define	QSPI_EVENTS_DMA_ABORTED_ABORTED_Generated (0x1UL)

#define	QSPI_CONFIG_TXBURSTLENGTH_ResetValue (0x00000008UL)

#define	QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Pos (0UL)

#define	QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Msk (0x1FUL << QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Pos)

#define	QSPI_CONFIG_RXBURSTLENGTH_ResetValue (0x00000008UL)

#define	QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Pos (0UL)

#define	QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Msk (0x1FUL << QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Pos)

#define	QSPI_CONFIG_RXTRANSFERLENGTH_ResetValue (0x00000010UL)

#define	QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Pos (0UL)

#define	QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Msk (0x3FFFFUL << QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Pos)

#define	QSPI_CONFIG_STOPON_ResetValue (0x00000003UL)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Pos (0UL)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Pos)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Disabled (0x0UL)

#define	QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Enabled (0x1UL)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Pos (1UL)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Msk (0x1UL << QSPI_CONFIG_STOPON_RXOVERFLOW_Pos)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Min (0x0UL)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Max (0x1UL)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Disabled (0x0UL)

#define	QSPI_CONFIG_STOPON_RXOVERFLOW_Enabled (0x1UL)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Pos (2UL)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Msk (0x1UL << QSPI_CONFIG_STOPON_INTERNALBUSERROR_Pos)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Min (0x0UL)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Max (0x1UL)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Disabled (0x0UL)

#define	QSPI_CONFIG_STOPON_INTERNALBUSERROR_Enabled (0x1UL)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Pos (3UL)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Msk (0x1UL << QSPI_CONFIG_STOPON_DMABUSERROR_Pos)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Min (0x0UL)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Max (0x1UL)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Disabled (0x0UL)

#define	QSPI_CONFIG_STOPON_DMABUSERROR_Enabled (0x1UL)

#define	QSPI_CONFIG_AXIMODE_ResetValue (0x00000000UL)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Pos (4UL)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Msk (0x1UL << QSPI_CONFIG_AXIMODE_AXIMODE_Pos)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Min (0x0UL)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Max (0x1UL)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Lite (0x0UL)

#define	QSPI_CONFIG_AXIMODE_AXIMODE_Full (0x1UL)

#define	QSPI_CONFIG_AXIMODE_MODE_Pos (5UL)

#define	QSPI_CONFIG_AXIMODE_MODE_Msk (0x1UL << QSPI_CONFIG_AXIMODE_MODE_Pos)

#define	QSPI_FORMAT_DFS_ResetValue (0x00000000UL)

#define	QSPI_FORMAT_DFS_DFS_Pos (0UL)

#define	QSPI_FORMAT_DFS_DFS_Msk (0x3FUL << QSPI_FORMAT_DFS_DFS_Pos)

#define	QSPI_FORMAT_BPP_ResetValue (0x00000000UL)

#define	QSPI_FORMAT_BPP_BPP_Pos (0UL)

#define	QSPI_FORMAT_BPP_BPP_Msk (0x3FUL << QSPI_FORMAT_BPP_BPP_Pos)

#define	QSPI_FORMAT_BPP_BPP_Min (0x0UL)

#define	QSPI_FORMAT_BPP_BPP_Max (0x10UL)

#define	QSPI_FORMAT_BPP_BPP_0 (0x00UL)

#define	QSPI_FORMAT_BPP_BPP_4 (0x04UL)

#define	QSPI_FORMAT_BPP_BPP_8 (0x08UL)

#define	QSPI_FORMAT_BPP_BPP_16 (0x10UL)

#define	QSPI_FORMAT_PIXELS_ResetValue (0x00000000UL)

#define	QSPI_FORMAT_PIXELS_PIXELS_Pos (0UL)

#define	QSPI_FORMAT_PIXELS_PIXELS_Msk (0x3FFFFUL << QSPI_FORMAT_PIXELS_PIXELS_Pos)

#define	QSPI_FORMAT_CILEN_ResetValue (0x00000000UL)

#define	QSPI_FORMAT_CILEN_CILEN_Pos (0UL)

#define	QSPI_FORMAT_CILEN_CILEN_Msk (0x3UL << QSPI_FORMAT_CILEN_CILEN_Pos)

#define	QSPI_FORMAT_BITORDER_ResetValue (0x00000000UL)

#define	QSPI_FORMAT_BITORDER_COMMAND_Pos (0UL)

#define	QSPI_FORMAT_BITORDER_COMMAND_Msk (0x1UL << QSPI_FORMAT_BITORDER_COMMAND_Pos)

#define	QSPI_FORMAT_BITORDER_DATA_Pos (1UL)

#define	QSPI_FORMAT_BITORDER_DATA_Msk (0x1UL << QSPI_FORMAT_BITORDER_DATA_Pos)

#define	QSPI_DMA_STATUS_BYTECOUNT_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Pos (0UL)

#define	QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Msk (0xFFFFFFFFUL << QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Pos)

#define	QSPI_DMA_STATUS_ATTRIBUTE_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Pos (0UL)

#define	QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Msk (0x3FUL << QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Pos)

#define	QSPI_DMA_STATUS_ADDRESS_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_ADDRESS_ADDRESS_Pos (0UL)

#define	QSPI_DMA_STATUS_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << QSPI_DMA_STATUS_ADDRESS_ADDRESS_Pos)

#define	QSPI_DMA_STATUS_JOBCOUNT_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Pos (0UL)

#define	QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Msk (0xFFFFFFFFUL << QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Pos)

#define	QSPI_DMA_STATUS_BUSERROR_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_Pos (0UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_Msk (0x7UL << QSPI_DMA_STATUS_BUSERROR_BUSERROR_Pos)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_Min (0x0UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_Max (0x4UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_NoError (0x0UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_ReadError (0x1UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_ReadDecodeError (0x2UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_WriteError (0x3UL)

#define	QSPI_DMA_STATUS_BUSERROR_BUSERROR_WriteDecodeError (0x4UL)

#define	QSPI_DMA_STATUS_FIFO_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Pos (0UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Msk (0x3UL << QSPI_DMA_STATUS_FIFO_RXFIFO_Pos)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Min (0x0UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Max (0x2UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Empty (0x0UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_NotEmpty (0x1UL)

#define	QSPI_DMA_STATUS_FIFO_RXFIFO_Full (0x2UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Pos (2UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Msk (0x3UL << QSPI_DMA_STATUS_FIFO_TXFIFO_Pos)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Min (0x0UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Max (0x2UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Empty (0x0UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_NotEmpty (0x1UL)

#define	QSPI_DMA_STATUS_FIFO_TXFIFO_Full (0x2UL)

#define	QSPI_DMA_STATUS_ACTIVE_ResetValue (0x00000000UL)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Pos (0UL)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Msk (0x1UL << QSPI_DMA_STATUS_ACTIVE_ACTIVE_Pos)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Min (0x0UL)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Max (0x1UL)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Idle (0x0UL)

#define	QSPI_DMA_STATUS_ACTIVE_ACTIVE_Active (0x1UL)

#define	QSPI_DMA_CONFIG_BUFFERFILL_ResetValue (0x00000000UL)

#define	QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Pos (0UL)

#define	QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Msk (0xFFUL << QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Pos)

#define	QSPI_DMA_CONFIG_LISTPTR_ResetValue (0x00000000UL)

#define	QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Pos (0UL)

#define	QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Msk (0xFFFFFFFFUL << QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Pos)

#define	QSPI_DMA_CONFIG_LISTPARTTHRESH_ResetValue (0x00000000UL)

#define	QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Pos (0UL)

#define	QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Msk (0xFFFFUL << QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Pos)

#define	QSPI_CORE_CORE_CTRLR0_ResetValue (0x00000007UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_Pos (0UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_Msk (0x1FUL << QSPI_CORE_CORE_CTRLR0_DFS_Pos)

#define	QSPI_CORE_CORE_CTRLR0_DFS_Min (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_Max (0x1FUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS04BIT (0x03UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS05BIT (0x04UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS06BIT (0x05UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS07BIT (0x06UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS08BIT (0x07UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS09BIT (0x08UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS10BIT (0x09UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS11BIT (0x0AUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS12BIT (0x0BUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS13BIT (0x0CUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS14BIT (0x0DUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS15BIT (0x0EUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS16BIT (0x0FUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS17BIT (0x10UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS18BIT (0x11UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS19BIT (0x12UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS20BIT (0x13UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS21BIT (0x14UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS22BIT (0x15UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS23BIT (0x16UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS24BIT (0x17UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS25BIT (0x18UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS26BIT (0x19UL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS27BIT (0x1AUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS28BIT (0x1BUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS29BIT (0x1CUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS30BIT (0x1DUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS31BIT (0x1EUL)

#define	QSPI_CORE_CORE_CTRLR0_DFS_DFS32BIT (0x1FUL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Pos (5UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Pos)

#define	QSPI_CORE_CORE_CTRLR0_FRF_Pos (6UL)

#define	QSPI_CORE_CORE_CTRLR0_FRF_Msk (0x3UL << QSPI_CORE_CORE_CTRLR0_FRF_Pos)

#define	QSPI_CORE_CORE_CTRLR0_FRF_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_FRF_Max (0x2UL)

#define	QSPI_CORE_CORE_CTRLR0_FRF_SPI (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_FRF_SSP (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_FRF_MICROWIRE (0x2UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_Pos (8UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SCPH_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_MIDDLEBIT (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPH_STARTBIT (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_Pos (9UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SCPOL_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVEHIGH (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVELOW (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_Pos (10UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_Msk (0x3UL << QSPI_CORE_CORE_CTRLR0_TMOD_Pos)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_Max (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_TXANDRX (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_TXONLY (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_RXONLY (0x2UL)

#define	QSPI_CORE_CORE_CTRLR0_TMOD_EEPROMREAD (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_Pos (12UL)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SLVOE_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_ENABLED (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SLVOE_DISABLED (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SRL_Pos (13UL)

#define	QSPI_CORE_CORE_CTRLR0_SRL_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SRL_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SRL_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SRL_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SRL_NORMALMODE (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SRL_TESTINGMODE (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_Pos (14UL)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SSTE_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_TOGGLEDISABLE (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SSTE_TOGGLEEN (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Pos (15UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Pos)

#define	QSPI_CORE_CORE_CTRLR0_CFS_Pos (16UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_Msk (0xFUL << QSPI_CORE_CORE_CTRLR0_CFS_Pos)

#define	QSPI_CORE_CORE_CTRLR0_CFS_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_Max (0xFUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE01BIT (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE02BIT (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE03BIT (0x2UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE04BIT (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE05BIT (0x4UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE06BIT (0x5UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE07BIT (0x6UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE08BIT (0x7UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE09BIT (0x8UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE10BIT (0x9UL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE11BIT (0xAUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE12BIT (0xBUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE13BIT (0xCUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE14BIT (0xDUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE15BIT (0xEUL)

#define	QSPI_CORE_CORE_CTRLR0_CFS_SIZE16BIT (0xFUL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Pos (20UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Msk (0x3UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_Pos (22UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_Msk (0x3UL << QSPI_CORE_CORE_CTRLR0_SPIFRF_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_Max (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_SPISTANDARD (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIDUAL (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIQUAD (0x2UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIOCTAL (0x3UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Pos (24UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_ENABLE (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Pos (25UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SPIDWSEN_ENABLE (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Pos (26UL)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Pos)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_ENABLE (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Pos (27UL)

#define	QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Msk (0xFUL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Pos (31UL)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Msk (0x1UL << QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Pos)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Min (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Max (0x1UL)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_TARGET (0x0UL)

#define	QSPI_CORE_CORE_CTRLR0_SQSPIISMST_CONTROLLER (0x1UL)

#define	QSPI_CORE_CORE_CTRLR1_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_CTRLR1_NDF_Pos (0UL)

#define	QSPI_CORE_CORE_CTRLR1_NDF_Msk (0xFFFFUL << QSPI_CORE_CORE_CTRLR1_NDF_Pos)

#define	QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Pos (16UL)

#define	QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Msk (0xFFFFUL << QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Pos)

#define	QSPI_CORE_CORE_SQSPIENR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Pos (0UL)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Msk (0x1UL << QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Pos)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Min (0x0UL)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Max (0x1UL)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_SQSPIENR_SQSPICEN_ENABLED (0x1UL)

#define	QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Pos (1UL)

#define	QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Pos)

#define	QSPI_CORE_CORE_MWCR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_MWCR_MWMOD_Pos (0UL)

#define	QSPI_CORE_CORE_MWCR_MWMOD_Msk (0x1UL << QSPI_CORE_CORE_MWCR_MWMOD_Pos)

#define	QSPI_CORE_CORE_MWCR_MWMOD_Min (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MWMOD_Max (0x1UL)

#define	QSPI_CORE_CORE_MWCR_MWMOD_NONSEQUENTIAL (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MWMOD_SEQUENTIAL (0x1UL)

#define	QSPI_CORE_CORE_MWCR_MDD_Pos (1UL)

#define	QSPI_CORE_CORE_MWCR_MDD_Msk (0x1UL << QSPI_CORE_CORE_MWCR_MDD_Pos)

#define	QSPI_CORE_CORE_MWCR_MDD_Min (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MDD_Max (0x1UL)

#define	QSPI_CORE_CORE_MWCR_MDD_RECEIVE (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MDD_TRANSMIT (0x1UL)

#define	QSPI_CORE_CORE_MWCR_MHS_Pos (2UL)

#define	QSPI_CORE_CORE_MWCR_MHS_Msk (0x1UL << QSPI_CORE_CORE_MWCR_MHS_Pos)

#define	QSPI_CORE_CORE_MWCR_MHS_Min (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MHS_Max (0x1UL)

#define	QSPI_CORE_CORE_MWCR_MHS_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_MWCR_MHS_ENABLED (0x1UL)

#define	QSPI_CORE_CORE_MWCR_RSVDMWCR_Pos (3UL)

#define	QSPI_CORE_CORE_MWCR_RSVDMWCR_Msk (0x1FFFFFFFUL << QSPI_CORE_CORE_MWCR_RSVDMWCR_Pos)

#define	QSPI_CORE_CORE_SER_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_SER_SER_Pos (0UL)

#define	QSPI_CORE_CORE_SER_SER_Msk (0xFUL << QSPI_CORE_CORE_SER_SER_Pos)

#define	QSPI_CORE_CORE_SER_RSVDSER_Pos (4UL)

#define	QSPI_CORE_CORE_SER_RSVDSER_Msk (0xFFFFFFFUL << QSPI_CORE_CORE_SER_RSVDSER_Pos)

#define	QSPI_CORE_CORE_BAUDR_ResetValue (0x00000002UL)

#define	QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Pos (0UL)

#define	QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Msk (0x1UL << QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Pos)

#define	QSPI_CORE_CORE_BAUDR_SCKDV_Pos (1UL)

#define	QSPI_CORE_CORE_BAUDR_SCKDV_Msk (0x7FFFUL << QSPI_CORE_CORE_BAUDR_SCKDV_Pos)

#define	QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Pos (16UL)

#define	QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Msk (0xFFFFUL << QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Pos)

#define	QSPI_CORE_CORE_TXFTLR_ResetValue (0x00080000UL)

#define	QSPI_CORE_CORE_TXFTLR_TFT_Pos (0UL)

#define	QSPI_CORE_CORE_TXFTLR_TFT_Msk (0xFUL << QSPI_CORE_CORE_TXFTLR_TFT_Pos)

#define	QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Pos (4UL)

#define	QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Msk (0xFFFUL << QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Pos)

#define	QSPI_CORE_CORE_TXFTLR_TXFTHR_Pos (16UL)

#define	QSPI_CORE_CORE_TXFTLR_TXFTHR_Msk (0xFUL << QSPI_CORE_CORE_TXFTLR_TXFTHR_Pos)

#define	QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Pos (20UL)

#define	QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Msk (0xFFFUL << QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Pos)

#define	QSPI_CORE_CORE_RXFTLR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RXFTLR_RFT_Pos (0UL)

#define	QSPI_CORE_CORE_RXFTLR_RFT_Msk (0xFUL << QSPI_CORE_CORE_RXFTLR_RFT_Pos)

#define	QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Pos (4UL)

#define	QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Msk (0xFFFFFFFUL << QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Pos)

#define	QSPI_CORE_CORE_TXFLR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_TXFLR_TXTFL_Pos (0UL)

#define	QSPI_CORE_CORE_TXFLR_TXTFL_Msk (0x1FUL << QSPI_CORE_CORE_TXFLR_TXTFL_Pos)

#define	QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Pos (5UL)

#define	QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Msk (0x7FFFFFFUL << QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Pos)

#define	QSPI_CORE_CORE_RXFLR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RXFLR_RXTFL_Pos (0UL)

#define	QSPI_CORE_CORE_RXFLR_RXTFL_Msk (0x1FUL << QSPI_CORE_CORE_RXFLR_RXTFL_Pos)

#define	QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Pos (5UL)

#define	QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Msk (0x7FFFFFFUL << QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Pos)

#define	QSPI_CORE_CORE_SR_ResetValue (0x00000006UL)

#define	QSPI_CORE_CORE_SR_BUSY_Pos (0UL)

#define	QSPI_CORE_CORE_SR_BUSY_Msk (0x1UL << QSPI_CORE_CORE_SR_BUSY_Pos)

#define	QSPI_CORE_CORE_SR_BUSY_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_BUSY_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_BUSY_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_SR_BUSY_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_SR_TFNF_Pos (1UL)

#define	QSPI_CORE_CORE_SR_TFNF_Msk (0x1UL << QSPI_CORE_CORE_SR_TFNF_Pos)

#define	QSPI_CORE_CORE_SR_TFNF_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_TFNF_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_TFNF_FULL (0x0UL)

#define	QSPI_CORE_CORE_SR_TFNF_NOTFULL (0x1UL)

#define	QSPI_CORE_CORE_SR_TFE_Pos (2UL)

#define	QSPI_CORE_CORE_SR_TFE_Msk (0x1UL << QSPI_CORE_CORE_SR_TFE_Pos)

#define	QSPI_CORE_CORE_SR_TFE_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_TFE_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_TFE_NOTEMPTY (0x0UL)

#define	QSPI_CORE_CORE_SR_TFE_EMPTY (0x1UL)

#define	QSPI_CORE_CORE_SR_RFNE_Pos (3UL)

#define	QSPI_CORE_CORE_SR_RFNE_Msk (0x1UL << QSPI_CORE_CORE_SR_RFNE_Pos)

#define	QSPI_CORE_CORE_SR_RFNE_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_RFNE_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_RFNE_EMPTY (0x0UL)

#define	QSPI_CORE_CORE_SR_RFNE_NOTEMPTY (0x1UL)

#define	QSPI_CORE_CORE_SR_RFF_Pos (4UL)

#define	QSPI_CORE_CORE_SR_RFF_Msk (0x1UL << QSPI_CORE_CORE_SR_RFF_Pos)

#define	QSPI_CORE_CORE_SR_RFF_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_RFF_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_RFF_NOTFULL (0x0UL)

#define	QSPI_CORE_CORE_SR_RFF_FULL (0x1UL)

#define	QSPI_CORE_CORE_SR_TXE_Pos (5UL)

#define	QSPI_CORE_CORE_SR_TXE_Msk (0x1UL << QSPI_CORE_CORE_SR_TXE_Pos)

#define	QSPI_CORE_CORE_SR_TXE_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_TXE_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_TXE_NOERROR (0x0UL)

#define	QSPI_CORE_CORE_SR_TXE_TXERROR (0x1UL)

#define	QSPI_CORE_CORE_SR_DCOL_Pos (6UL)

#define	QSPI_CORE_CORE_SR_DCOL_Msk (0x1UL << QSPI_CORE_CORE_SR_DCOL_Pos)

#define	QSPI_CORE_CORE_SR_DCOL_Min (0x0UL)

#define	QSPI_CORE_CORE_SR_DCOL_Max (0x1UL)

#define	QSPI_CORE_CORE_SR_DCOL_NOERRORCONDITION (0x0UL)

#define	QSPI_CORE_CORE_SR_DCOL_TXCOLLISIONERROR (0x1UL)

#define	QSPI_CORE_CORE_SR_RSVDSR_Pos (7UL)

#define	QSPI_CORE_CORE_SR_RSVDSR_Msk (0xFFUL << QSPI_CORE_CORE_SR_RSVDSR_Pos)

#define	QSPI_CORE_CORE_SR_CMPLTDDF_Pos (15UL)

#define	QSPI_CORE_CORE_SR_CMPLTDDF_Msk (0x1FFFFUL << QSPI_CORE_CORE_SR_CMPLTDDF_Pos)

#define	QSPI_CORE_CORE_IMR_ResetValue (0x0000043FUL)

#define	QSPI_CORE_CORE_IMR_TXEIM_Pos (0UL)

#define	QSPI_CORE_CORE_IMR_TXEIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_TXEIM_Pos)

#define	QSPI_CORE_CORE_IMR_TXEIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXEIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_TXEIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXEIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_TXOIM_Pos (1UL)

#define	QSPI_CORE_CORE_IMR_TXOIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_TXOIM_Pos)

#define	QSPI_CORE_CORE_IMR_TXOIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXOIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_TXOIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXOIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXUIM_Pos (2UL)

#define	QSPI_CORE_CORE_IMR_RXUIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_RXUIM_Pos)

#define	QSPI_CORE_CORE_IMR_RXUIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXUIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXUIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXUIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXOIM_Pos (3UL)

#define	QSPI_CORE_CORE_IMR_RXOIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_RXOIM_Pos)

#define	QSPI_CORE_CORE_IMR_RXOIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXOIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXOIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXOIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXFIM_Pos (4UL)

#define	QSPI_CORE_CORE_IMR_RXFIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_RXFIM_Pos)

#define	QSPI_CORE_CORE_IMR_RXFIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXFIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_RXFIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_RXFIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_MSTIM_Pos (5UL)

#define	QSPI_CORE_CORE_IMR_MSTIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_MSTIM_Pos)

#define	QSPI_CORE_CORE_IMR_MSTIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_MSTIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_MSTIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_MSTIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_XRXOIM_Pos (6UL)

#define	QSPI_CORE_CORE_IMR_XRXOIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_XRXOIM_Pos)

#define	QSPI_CORE_CORE_IMR_XRXOIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_XRXOIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_XRXOIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_XRXOIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_TXUIM_Pos (7UL)

#define	QSPI_CORE_CORE_IMR_TXUIM_Msk (0x1UL << QSPI_CORE_CORE_IMR_TXUIM_Pos)

#define	QSPI_CORE_CORE_IMR_TXUIM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXUIM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_TXUIM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_TXUIM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_AXIEM_Pos (8UL)

#define	QSPI_CORE_CORE_IMR_AXIEM_Msk (0x1UL << QSPI_CORE_CORE_IMR_AXIEM_Pos)

#define	QSPI_CORE_CORE_IMR_AXIEM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_AXIEM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_AXIEM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_AXIEM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_RSVD9IMR_Pos (9UL)

#define	QSPI_CORE_CORE_IMR_RSVD9IMR_Msk (0x1UL << QSPI_CORE_CORE_IMR_RSVD9IMR_Pos)

#define	QSPI_CORE_CORE_IMR_SPITEM_Pos (10UL)

#define	QSPI_CORE_CORE_IMR_SPITEM_Msk (0x1UL << QSPI_CORE_CORE_IMR_SPITEM_Pos)

#define	QSPI_CORE_CORE_IMR_SPITEM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_SPITEM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_SPITEM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_SPITEM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_DONEM_Pos (11UL)

#define	QSPI_CORE_CORE_IMR_DONEM_Msk (0x1UL << QSPI_CORE_CORE_IMR_DONEM_Pos)

#define	QSPI_CORE_CORE_IMR_DONEM_Min (0x0UL)

#define	QSPI_CORE_CORE_IMR_DONEM_Max (0x1UL)

#define	QSPI_CORE_CORE_IMR_DONEM_MASKED (0x0UL)

#define	QSPI_CORE_CORE_IMR_DONEM_UNMASKED (0x1UL)

#define	QSPI_CORE_CORE_IMR_RSVD1231IMR_Pos (12UL)

#define	QSPI_CORE_CORE_IMR_RSVD1231IMR_Msk (0xFFFFFUL << QSPI_CORE_CORE_IMR_RSVD1231IMR_Pos)

#define	QSPI_CORE_CORE_ISR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_ISR_TXEIS_Pos (0UL)

#define	QSPI_CORE_CORE_ISR_TXEIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_TXEIS_Pos)

#define	QSPI_CORE_CORE_ISR_TXEIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXEIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_TXEIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXEIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_TXOIS_Pos (1UL)

#define	QSPI_CORE_CORE_ISR_TXOIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_TXOIS_Pos)

#define	QSPI_CORE_CORE_ISR_TXOIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXOIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_TXOIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXOIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXUIS_Pos (2UL)

#define	QSPI_CORE_CORE_ISR_RXUIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_RXUIS_Pos)

#define	QSPI_CORE_CORE_ISR_RXUIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXUIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXUIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXUIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXOIS_Pos (3UL)

#define	QSPI_CORE_CORE_ISR_RXOIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_RXOIS_Pos)

#define	QSPI_CORE_CORE_ISR_RXOIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXOIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXOIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXOIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXFIS_Pos (4UL)

#define	QSPI_CORE_CORE_ISR_RXFIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_RXFIS_Pos)

#define	QSPI_CORE_CORE_ISR_RXFIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXFIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_RXFIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_RXFIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_MSTIS_Pos (5UL)

#define	QSPI_CORE_CORE_ISR_MSTIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_MSTIS_Pos)

#define	QSPI_CORE_CORE_ISR_MSTIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_MSTIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_MSTIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_MSTIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_XRXOIS_Pos (6UL)

#define	QSPI_CORE_CORE_ISR_XRXOIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_XRXOIS_Pos)

#define	QSPI_CORE_CORE_ISR_XRXOIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_XRXOIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_XRXOIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_XRXOIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_TXUIS_Pos (7UL)

#define	QSPI_CORE_CORE_ISR_TXUIS_Msk (0x1UL << QSPI_CORE_CORE_ISR_TXUIS_Pos)

#define	QSPI_CORE_CORE_ISR_TXUIS_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXUIS_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_TXUIS_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_TXUIS_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_AXIES_Pos (8UL)

#define	QSPI_CORE_CORE_ISR_AXIES_Msk (0x1UL << QSPI_CORE_CORE_ISR_AXIES_Pos)

#define	QSPI_CORE_CORE_ISR_AXIES_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_AXIES_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_AXIES_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_AXIES_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_RSVD9RISR_Pos (9UL)

#define	QSPI_CORE_CORE_ISR_RSVD9RISR_Msk (0x1UL << QSPI_CORE_CORE_ISR_RSVD9RISR_Pos)

#define	QSPI_CORE_CORE_ISR_SPITES_Pos (10UL)

#define	QSPI_CORE_CORE_ISR_SPITES_Msk (0x1UL << QSPI_CORE_CORE_ISR_SPITES_Pos)

#define	QSPI_CORE_CORE_ISR_SPITES_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_SPITES_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_SPITES_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_SPITES_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_DONES_Pos (11UL)

#define	QSPI_CORE_CORE_ISR_DONES_Msk (0x1UL << QSPI_CORE_CORE_ISR_DONES_Pos)

#define	QSPI_CORE_CORE_ISR_DONES_Min (0x0UL)

#define	QSPI_CORE_CORE_ISR_DONES_Max (0x1UL)

#define	QSPI_CORE_CORE_ISR_DONES_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_ISR_DONES_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_ISR_RSVD1231RISR_Pos (12UL)

#define	QSPI_CORE_CORE_ISR_RSVD1231RISR_Msk (0xFFFFFUL << QSPI_CORE_CORE_ISR_RSVD1231RISR_Pos)

#define	QSPI_CORE_CORE_RISR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RISR_TXEIR_Pos (0UL)

#define	QSPI_CORE_CORE_RISR_TXEIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_TXEIR_Pos)

#define	QSPI_CORE_CORE_RISR_TXEIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXEIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_TXEIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXEIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_TXOIR_Pos (1UL)

#define	QSPI_CORE_CORE_RISR_TXOIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_TXOIR_Pos)

#define	QSPI_CORE_CORE_RISR_TXOIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXOIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_TXOIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXOIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXUIR_Pos (2UL)

#define	QSPI_CORE_CORE_RISR_RXUIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_RXUIR_Pos)

#define	QSPI_CORE_CORE_RISR_RXUIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXUIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXUIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXUIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXOIR_Pos (3UL)

#define	QSPI_CORE_CORE_RISR_RXOIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_RXOIR_Pos)

#define	QSPI_CORE_CORE_RISR_RXOIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXOIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXOIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXOIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXFIR_Pos (4UL)

#define	QSPI_CORE_CORE_RISR_RXFIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_RXFIR_Pos)

#define	QSPI_CORE_CORE_RISR_RXFIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXFIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_RXFIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_RXFIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_MSTIR_Pos (5UL)

#define	QSPI_CORE_CORE_RISR_MSTIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_MSTIR_Pos)

#define	QSPI_CORE_CORE_RISR_MSTIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_MSTIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_MSTIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_MSTIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_XRXOIR_Pos (6UL)

#define	QSPI_CORE_CORE_RISR_XRXOIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_XRXOIR_Pos)

#define	QSPI_CORE_CORE_RISR_XRXOIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_XRXOIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_XRXOIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_XRXOIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_TXUIR_Pos (7UL)

#define	QSPI_CORE_CORE_RISR_TXUIR_Msk (0x1UL << QSPI_CORE_CORE_RISR_TXUIR_Pos)

#define	QSPI_CORE_CORE_RISR_TXUIR_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXUIR_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_TXUIR_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_TXUIR_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_AXIER_Pos (8UL)

#define	QSPI_CORE_CORE_RISR_AXIER_Msk (0x1UL << QSPI_CORE_CORE_RISR_AXIER_Pos)

#define	QSPI_CORE_CORE_RISR_AXIER_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_AXIER_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_AXIER_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_AXIER_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_RSVD9RISR_Pos (9UL)

#define	QSPI_CORE_CORE_RISR_RSVD9RISR_Msk (0x1UL << QSPI_CORE_CORE_RISR_RSVD9RISR_Pos)

#define	QSPI_CORE_CORE_RISR_SPITER_Pos (10UL)

#define	QSPI_CORE_CORE_RISR_SPITER_Msk (0x1UL << QSPI_CORE_CORE_RISR_SPITER_Pos)

#define	QSPI_CORE_CORE_RISR_SPITER_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_SPITER_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_SPITER_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_SPITER_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_DONER_Pos (11UL)

#define	QSPI_CORE_CORE_RISR_DONER_Msk (0x1UL << QSPI_CORE_CORE_RISR_DONER_Pos)

#define	QSPI_CORE_CORE_RISR_DONER_Min (0x0UL)

#define	QSPI_CORE_CORE_RISR_DONER_Max (0x1UL)

#define	QSPI_CORE_CORE_RISR_DONER_INACTIVE (0x0UL)

#define	QSPI_CORE_CORE_RISR_DONER_ACTIVE (0x1UL)

#define	QSPI_CORE_CORE_RISR_RSVD1231RISR_Pos (12UL)

#define	QSPI_CORE_CORE_RISR_RSVD1231RISR_Msk (0xFFFFFUL << QSPI_CORE_CORE_RISR_RSVD1231RISR_Pos)

#define	QSPI_CORE_CORE_TXEICR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_TXEICR_TXEICR_Pos (0UL)

#define	QSPI_CORE_CORE_TXEICR_TXEICR_Msk (0x1UL << QSPI_CORE_CORE_TXEICR_TXEICR_Pos)

#define	QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Pos (1UL)

#define	QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Pos)

#define	QSPI_CORE_CORE_RXOICR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RXOICR_RXOICR_Pos (0UL)

#define	QSPI_CORE_CORE_RXOICR_RXOICR_Msk (0x1UL << QSPI_CORE_CORE_RXOICR_RXOICR_Pos)

#define	QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Pos (1UL)

#define	QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Pos)

#define	QSPI_CORE_CORE_RXUICR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RXUICR_RXUICR_Pos (0UL)

#define	QSPI_CORE_CORE_RXUICR_RXUICR_Msk (0x1UL << QSPI_CORE_CORE_RXUICR_RXUICR_Pos)

#define	QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Pos (1UL)

#define	QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Pos)

#define	QSPI_CORE_CORE_MSTICR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_MSTICR_MSTICR_Pos (0UL)

#define	QSPI_CORE_CORE_MSTICR_MSTICR_Msk (0x1UL << QSPI_CORE_CORE_MSTICR_MSTICR_Pos)

#define	QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Pos (1UL)

#define	QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Pos)

#define	QSPI_CORE_CORE_ICR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_ICR_ICR_Pos (0UL)

#define	QSPI_CORE_CORE_ICR_ICR_Msk (0x1UL << QSPI_CORE_CORE_ICR_ICR_Pos)

#define	QSPI_CORE_CORE_ICR_RSVDICR_Pos (1UL)

#define	QSPI_CORE_CORE_ICR_RSVDICR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_ICR_RSVDICR_Pos)

#define	QSPI_CORE_CORE_DMACR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_DMACR_RDMAE_Pos (0UL)

#define	QSPI_CORE_CORE_DMACR_RDMAE_Msk (0x1UL << QSPI_CORE_CORE_DMACR_RDMAE_Pos)

#define	QSPI_CORE_CORE_DMACR_RDMAE_Min (0x0UL)

#define	QSPI_CORE_CORE_DMACR_RDMAE_Max (0x1UL)

#define	QSPI_CORE_CORE_DMACR_RDMAE_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_DMACR_RDMAE_ENABLED (0x1UL)

#define	QSPI_CORE_CORE_DMACR_TDMAE_Pos (1UL)

#define	QSPI_CORE_CORE_DMACR_TDMAE_Msk (0x1UL << QSPI_CORE_CORE_DMACR_TDMAE_Pos)

#define	QSPI_CORE_CORE_DMACR_TDMAE_Min (0x0UL)

#define	QSPI_CORE_CORE_DMACR_TDMAE_Max (0x1UL)

#define	QSPI_CORE_CORE_DMACR_TDMAE_DISABLE (0x0UL)

#define	QSPI_CORE_CORE_DMACR_TDMAE_ENABLED (0x1UL)

#define	QSPI_CORE_CORE_DMACR_IDMAE_Pos (2UL)

#define	QSPI_CORE_CORE_DMACR_IDMAE_Msk (0x1UL << QSPI_CORE_CORE_DMACR_IDMAE_Pos)

#define	QSPI_CORE_CORE_DMACR_ATW_Pos (3UL)

#define	QSPI_CORE_CORE_DMACR_ATW_Msk (0x3UL << QSPI_CORE_CORE_DMACR_ATW_Pos)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR5_Pos (5UL)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR5_Msk (0x1UL << QSPI_CORE_CORE_DMACR_RSVDDMACR5_Pos)

#define	QSPI_CORE_CORE_DMACR_AINC_Pos (6UL)

#define	QSPI_CORE_CORE_DMACR_AINC_Msk (0x1UL << QSPI_CORE_CORE_DMACR_AINC_Pos)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR7_Pos (7UL)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR7_Msk (0x1UL << QSPI_CORE_CORE_DMACR_RSVDDMACR7_Pos)

#define	QSPI_CORE_CORE_DMACR_ACACHE_Pos (8UL)

#define	QSPI_CORE_CORE_DMACR_ACACHE_Msk (0xFUL << QSPI_CORE_CORE_DMACR_ACACHE_Pos)

#define	QSPI_CORE_CORE_DMACR_APROT_Pos (12UL)

#define	QSPI_CORE_CORE_DMACR_APROT_Msk (0x7UL << QSPI_CORE_CORE_DMACR_APROT_Pos)

#define	QSPI_CORE_CORE_DMACR_AID_Pos (15UL)

#define	QSPI_CORE_CORE_DMACR_AID_Msk (0x3FUL << QSPI_CORE_CORE_DMACR_AID_Pos)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR_Pos (21UL)

#define	QSPI_CORE_CORE_DMACR_RSVDDMACR_Msk (0x7FFUL << QSPI_CORE_CORE_DMACR_RSVDDMACR_Pos)

#define	QSPI_CORE_CORE_DMATDLR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_DMATDLR_DMATDL_Pos (0UL)

#define	QSPI_CORE_CORE_DMATDLR_DMATDL_Msk (0xFUL << QSPI_CORE_CORE_DMATDLR_DMATDL_Pos)

#define	QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Pos (4UL)

#define	QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Msk (0xFFFFFFFUL << QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Pos)

#define	QSPI_CORE_CORE_DMARDLR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_DMARDLR_DMARDL_Pos (0UL)

#define	QSPI_CORE_CORE_DMARDLR_DMARDL_Msk (0xFUL << QSPI_CORE_CORE_DMARDLR_DMARDL_Pos)

#define	QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Pos (4UL)

#define	QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Msk (0xFFFFFFFUL << QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Pos)

#define	QSPI_CORE_CORE_IDR_ResetValue (0x51535049UL)

#define	QSPI_CORE_CORE_IDR_IDCODE_Pos (0UL)

#define	QSPI_CORE_CORE_IDR_IDCODE_Msk (0xFFFFFFFFUL << QSPI_CORE_CORE_IDR_IDCODE_Pos)

#define	QSPI_CORE_CORE_SQSPICVERSIONID_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Pos (0UL)

#define	QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Msk (0xFFFFFFFFUL << QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Pos)

#define	QSPI_CORE_CORE_DR_MaxCount (36UL)

#define	QSPI_CORE_CORE_DR_MaxIndex (35UL)

#define	QSPI_CORE_CORE_DR_MinIndex (0UL)

#define	QSPI_CORE_CORE_DR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_DR_DR_Pos (0UL)

#define	QSPI_CORE_CORE_DR_DR_Msk (0xFFFFFFFFUL << QSPI_CORE_CORE_DR_DR_Pos)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Pos (0UL)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Msk (0xFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Pos)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Pos (8UL)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Msk (0xFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Pos)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Pos (16UL)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Msk (0x1UL << QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Pos)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Pos (17UL)

#define	QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Msk (0x7FFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_ResetValue (0x40000200UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Pos (0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Msk (0x3UL << QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Min (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Max (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT0 (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT1 (0x1UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT2 (0x2UL)

#define	QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT3 (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_Pos (2UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_Msk (0xFUL << QSPI_CORE_CORE_SPICTRLR0_ADDRL_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_Min (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_Max (0xFUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL0 (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL4 (0x1UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL8 (0x2UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL12 (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL16 (0x4UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL20 (0x5UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL24 (0x6UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL28 (0x7UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL32 (0x8UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL36 (0x9UL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL40 (0xAUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL44 (0xBUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL48 (0xCUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL52 (0xDUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL56 (0xEUL)

#define	QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL60 (0xFUL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Pos (6UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Pos (7UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_Pos (8UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_Msk (0x3UL << QSPI_CORE_CORE_SPICTRLR0_INSTL_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_Min (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_Max (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL0 (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL4 (0x1UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL8 (0x2UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL16 (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Pos (10UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Pos (11UL)

#define	QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Msk (0x1FUL << QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Pos (16UL)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Pos (17UL)

#define	QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Pos (18UL)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Pos (19UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Pos (20UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Pos (21UL)

#define	QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Pos (22UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Pos (23UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Pos (24UL)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Pos (25UL)

#define	QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Pos (26UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Msk (0x3UL << QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Min (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Max (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL2 (0x0UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL4 (0x1UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL8 (0x2UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL16 (0x3UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Pos (28UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Pos (29UL)

#define	QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Pos (30UL)

#define	QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Pos)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Pos (31UL)

#define	QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Msk (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_SPICTRLR1_DYNWS_Pos (0UL)

#define	QSPI_CORE_CORE_SPICTRLR1_DYNWS_Msk (0x7UL << QSPI_CORE_CORE_SPICTRLR1_DYNWS_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Pos (3UL)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Msk (0x1FUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_MAXWS_Pos (8UL)

#define	QSPI_CORE_CORE_SPICTRLR1_MAXWS_Msk (0xFUL << QSPI_CORE_CORE_SPICTRLR1_MAXWS_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Pos (12UL)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Msk (0xFUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Pos (16UL)

#define	QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Msk (0xFUL << QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Pos)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Pos (20UL)

#define	QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Msk (0xFFFUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Pos)

#define	QSPI_CORE_CORE_SPITECR_ResetValue (0x00000000UL)

#define	QSPI_CORE_CORE_SPITECR_SPITECR_Pos (0UL)

#define	QSPI_CORE_CORE_SPITECR_SPITECR_Msk (0x1UL << QSPI_CORE_CORE_SPITECR_SPITECR_Pos)

#define	QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Pos (1UL)

#define	QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Msk (0x7FFFFFFFUL << QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Pos)

#define	QSPI_SPSYNC_AUX_MaxCount (4UL)

#define	QSPI_SPSYNC_AUX_MaxIndex (3UL)

#define	QSPI_SPSYNC_AUX_MinIndex (0UL)

#define	QSPI_SPSYNC_AUX_ResetValue (0x00000000UL)

#define	QSPI_SPSYNC_AUX_AUX_Pos (0UL)

#define	QSPI_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << QSPI_SPSYNC_AUX_AUX_Pos)

#define	QSPI_TASKS_START_ResetValue (0x00000000UL)

#define	QSPI_TASKS_START_TASKS_START_Pos (0UL)

#define	QSPI_TASKS_START_TASKS_START_Msk (0x1UL << QSPI_TASKS_START_TASKS_START_Pos)

#define	QSPI_TASKS_START_TASKS_START_Min (0x1UL)

#define	QSPI_TASKS_START_TASKS_START_Max (0x1UL)

#define	QSPI_TASKS_START_TASKS_START_Trigger (0x1UL)

#define	QSPI_TASKS_RESET_ResetValue (0x00000000UL)

#define	QSPI_TASKS_RESET_TASKS_RESET_Pos (0UL)

#define	QSPI_TASKS_RESET_TASKS_RESET_Msk (0x1UL << QSPI_TASKS_RESET_TASKS_RESET_Pos)

#define	QSPI_TASKS_RESET_TASKS_RESET_Min (0x1UL)

#define	QSPI_TASKS_RESET_TASKS_RESET_Max (0x1UL)

#define	QSPI_TASKS_RESET_TASKS_RESET_Trigger (0x1UL)

#define	QSPI_EVENTS_CORE_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_Pos (0UL)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << QSPI_EVENTS_CORE_EVENTS_CORE_Pos)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_Min (0x0UL)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_Max (0x1UL)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL)

#define	QSPI_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL)

#define	QSPI_EVENTS_IDLE_ResetValue (0x00000000UL)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos (0UL)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_Msk (0x1UL << QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_Min (0x0UL)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_Max (0x1UL)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_NotGenerated (0x0UL)

#define	QSPI_EVENTS_IDLE_EVENTS_IDLE_Generated (0x1UL)

#define	QSPI_SHORTS_ResetValue (0x00000000UL)

#define	QSPI_SHORTS_DMA_DONE_START_Pos (0UL)

#define	QSPI_SHORTS_DMA_DONE_START_Msk (0x1UL << QSPI_SHORTS_DMA_DONE_START_Pos)

#define	QSPI_SHORTS_DMA_DONE_START_Min (0x0UL)

#define	QSPI_SHORTS_DMA_DONE_START_Max (0x1UL)

#define	QSPI_SHORTS_DMA_DONE_START_Disabled (0x0UL)

#define	QSPI_SHORTS_DMA_DONE_START_Enabled (0x1UL)

#define	QSPI_INTEN_ResetValue (0x00000000UL)

#define	QSPI_INTEN_CORE_Pos (0UL)

#define	QSPI_INTEN_CORE_Msk (0x1UL << QSPI_INTEN_CORE_Pos)

#define	QSPI_INTEN_CORE_Min (0x0UL)

#define	QSPI_INTEN_CORE_Max (0x1UL)

#define	QSPI_INTEN_CORE_Disabled (0x0UL)

#define	QSPI_INTEN_CORE_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONELIST_Pos (1UL)

#define	QSPI_INTEN_DMADONELIST_Msk (0x1UL << QSPI_INTEN_DMADONELIST_Pos)

#define	QSPI_INTEN_DMADONELIST_Min (0x0UL)

#define	QSPI_INTEN_DMADONELIST_Max (0x1UL)

#define	QSPI_INTEN_DMADONELIST_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONELIST_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONELISTPART_Pos (2UL)

#define	QSPI_INTEN_DMADONELISTPART_Msk (0x1UL << QSPI_INTEN_DMADONELISTPART_Pos)

#define	QSPI_INTEN_DMADONELISTPART_Min (0x0UL)

#define	QSPI_INTEN_DMADONELISTPART_Max (0x1UL)

#define	QSPI_INTEN_DMADONELISTPART_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONELISTPART_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONESELECTJOB_Pos (3UL)

#define	QSPI_INTEN_DMADONESELECTJOB_Msk (0x1UL << QSPI_INTEN_DMADONESELECTJOB_Pos)

#define	QSPI_INTEN_DMADONESELECTJOB_Min (0x0UL)

#define	QSPI_INTEN_DMADONESELECTJOB_Max (0x1UL)

#define	QSPI_INTEN_DMADONESELECTJOB_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONESELECTJOB_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONEDATA_Pos (4UL)

#define	QSPI_INTEN_DMADONEDATA_Msk (0x1UL << QSPI_INTEN_DMADONEDATA_Pos)

#define	QSPI_INTEN_DMADONEDATA_Min (0x0UL)

#define	QSPI_INTEN_DMADONEDATA_Max (0x1UL)

#define	QSPI_INTEN_DMADONEDATA_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONEDATA_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONEJOB_Pos (5UL)

#define	QSPI_INTEN_DMADONEJOB_Msk (0x1UL << QSPI_INTEN_DMADONEJOB_Pos)

#define	QSPI_INTEN_DMADONEJOB_Min (0x0UL)

#define	QSPI_INTEN_DMADONEJOB_Max (0x1UL)

#define	QSPI_INTEN_DMADONEJOB_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONEJOB_Enabled (0x1UL)

#define	QSPI_INTEN_DMAERROR_Pos (6UL)

#define	QSPI_INTEN_DMAERROR_Msk (0x1UL << QSPI_INTEN_DMAERROR_Pos)

#define	QSPI_INTEN_DMAERROR_Min (0x0UL)

#define	QSPI_INTEN_DMAERROR_Max (0x1UL)

#define	QSPI_INTEN_DMAERROR_Disabled (0x0UL)

#define	QSPI_INTEN_DMAERROR_Enabled (0x1UL)

#define	QSPI_INTEN_DMAPAUSED_Pos (7UL)

#define	QSPI_INTEN_DMAPAUSED_Msk (0x1UL << QSPI_INTEN_DMAPAUSED_Pos)

#define	QSPI_INTEN_DMAPAUSED_Min (0x0UL)

#define	QSPI_INTEN_DMAPAUSED_Max (0x1UL)

#define	QSPI_INTEN_DMAPAUSED_Disabled (0x0UL)

#define	QSPI_INTEN_DMAPAUSED_Enabled (0x1UL)

#define	QSPI_INTEN_DMARESET_Pos (8UL)

#define	QSPI_INTEN_DMARESET_Msk (0x1UL << QSPI_INTEN_DMARESET_Pos)

#define	QSPI_INTEN_DMARESET_Min (0x0UL)

#define	QSPI_INTEN_DMARESET_Max (0x1UL)

#define	QSPI_INTEN_DMARESET_Disabled (0x0UL)

#define	QSPI_INTEN_DMARESET_Enabled (0x1UL)

#define	QSPI_INTEN_DMADONE_Pos (9UL)

#define	QSPI_INTEN_DMADONE_Msk (0x1UL << QSPI_INTEN_DMADONE_Pos)

#define	QSPI_INTEN_DMADONE_Min (0x0UL)

#define	QSPI_INTEN_DMADONE_Max (0x1UL)

#define	QSPI_INTEN_DMADONE_Disabled (0x0UL)

#define	QSPI_INTEN_DMADONE_Enabled (0x1UL)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos (10UL)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Disabled (0x0UL)

#define	QSPI_INTEN_DMATXUNEXPECTEDIDLE_Enabled (0x1UL)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Pos (11UL)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Msk (0x1UL << QSPI_INTEN_DMAINTERNALBUSERROR_Pos)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Min (0x0UL)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Max (0x1UL)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Disabled (0x0UL)

#define	QSPI_INTEN_DMAINTERNALBUSERROR_Enabled (0x1UL)

#define	QSPI_INTEN_DMAABORTED_Pos (12UL)

#define	QSPI_INTEN_DMAABORTED_Msk (0x1UL << QSPI_INTEN_DMAABORTED_Pos)

#define	QSPI_INTEN_DMAABORTED_Min (0x0UL)

#define	QSPI_INTEN_DMAABORTED_Max (0x1UL)

#define	QSPI_INTEN_DMAABORTED_Disabled (0x0UL)

#define	QSPI_INTEN_DMAABORTED_Enabled (0x1UL)

#define	QSPI_INTEN_IDLE_Pos (13UL)

#define	QSPI_INTEN_IDLE_Msk (0x1UL << QSPI_INTEN_IDLE_Pos)

#define	QSPI_INTEN_IDLE_Min (0x0UL)

#define	QSPI_INTEN_IDLE_Max (0x1UL)

#define	QSPI_INTEN_IDLE_Disabled (0x0UL)

#define	QSPI_INTEN_IDLE_Enabled (0x1UL)

#define	QSPI_INTENSET_ResetValue (0x00000000UL)

#define	QSPI_INTENSET_CORE_Pos (0UL)

#define	QSPI_INTENSET_CORE_Msk (0x1UL << QSPI_INTENSET_CORE_Pos)

#define	QSPI_INTENSET_CORE_Min (0x0UL)

#define	QSPI_INTENSET_CORE_Max (0x1UL)

#define	QSPI_INTENSET_CORE_Set (0x1UL)

#define	QSPI_INTENSET_CORE_Disabled (0x0UL)

#define	QSPI_INTENSET_CORE_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONELIST_Pos (1UL)

#define	QSPI_INTENSET_DMADONELIST_Msk (0x1UL << QSPI_INTENSET_DMADONELIST_Pos)

#define	QSPI_INTENSET_DMADONELIST_Min (0x0UL)

#define	QSPI_INTENSET_DMADONELIST_Max (0x1UL)

#define	QSPI_INTENSET_DMADONELIST_Set (0x1UL)

#define	QSPI_INTENSET_DMADONELIST_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONELIST_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONELISTPART_Pos (2UL)

#define	QSPI_INTENSET_DMADONELISTPART_Msk (0x1UL << QSPI_INTENSET_DMADONELISTPART_Pos)

#define	QSPI_INTENSET_DMADONELISTPART_Min (0x0UL)

#define	QSPI_INTENSET_DMADONELISTPART_Max (0x1UL)

#define	QSPI_INTENSET_DMADONELISTPART_Set (0x1UL)

#define	QSPI_INTENSET_DMADONELISTPART_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONELISTPART_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Pos (3UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Msk (0x1UL << QSPI_INTENSET_DMADONESELECTJOB_Pos)

#define	QSPI_INTENSET_DMADONESELECTJOB_Min (0x0UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Max (0x1UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Set (0x1UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONESELECTJOB_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONEDATA_Pos (4UL)

#define	QSPI_INTENSET_DMADONEDATA_Msk (0x1UL << QSPI_INTENSET_DMADONEDATA_Pos)

#define	QSPI_INTENSET_DMADONEDATA_Min (0x0UL)

#define	QSPI_INTENSET_DMADONEDATA_Max (0x1UL)

#define	QSPI_INTENSET_DMADONEDATA_Set (0x1UL)

#define	QSPI_INTENSET_DMADONEDATA_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONEDATA_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONEJOB_Pos (5UL)

#define	QSPI_INTENSET_DMADONEJOB_Msk (0x1UL << QSPI_INTENSET_DMADONEJOB_Pos)

#define	QSPI_INTENSET_DMADONEJOB_Min (0x0UL)

#define	QSPI_INTENSET_DMADONEJOB_Max (0x1UL)

#define	QSPI_INTENSET_DMADONEJOB_Set (0x1UL)

#define	QSPI_INTENSET_DMADONEJOB_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONEJOB_Enabled (0x1UL)

#define	QSPI_INTENSET_DMAERROR_Pos (6UL)

#define	QSPI_INTENSET_DMAERROR_Msk (0x1UL << QSPI_INTENSET_DMAERROR_Pos)

#define	QSPI_INTENSET_DMAERROR_Min (0x0UL)

#define	QSPI_INTENSET_DMAERROR_Max (0x1UL)

#define	QSPI_INTENSET_DMAERROR_Set (0x1UL)

#define	QSPI_INTENSET_DMAERROR_Disabled (0x0UL)

#define	QSPI_INTENSET_DMAERROR_Enabled (0x1UL)

#define	QSPI_INTENSET_DMAPAUSED_Pos (7UL)

#define	QSPI_INTENSET_DMAPAUSED_Msk (0x1UL << QSPI_INTENSET_DMAPAUSED_Pos)

#define	QSPI_INTENSET_DMAPAUSED_Min (0x0UL)

#define	QSPI_INTENSET_DMAPAUSED_Max (0x1UL)

#define	QSPI_INTENSET_DMAPAUSED_Set (0x1UL)

#define	QSPI_INTENSET_DMAPAUSED_Disabled (0x0UL)

#define	QSPI_INTENSET_DMAPAUSED_Enabled (0x1UL)

#define	QSPI_INTENSET_DMARESET_Pos (8UL)

#define	QSPI_INTENSET_DMARESET_Msk (0x1UL << QSPI_INTENSET_DMARESET_Pos)

#define	QSPI_INTENSET_DMARESET_Min (0x0UL)

#define	QSPI_INTENSET_DMARESET_Max (0x1UL)

#define	QSPI_INTENSET_DMARESET_Set (0x1UL)

#define	QSPI_INTENSET_DMARESET_Disabled (0x0UL)

#define	QSPI_INTENSET_DMARESET_Enabled (0x1UL)

#define	QSPI_INTENSET_DMADONE_Pos (9UL)

#define	QSPI_INTENSET_DMADONE_Msk (0x1UL << QSPI_INTENSET_DMADONE_Pos)

#define	QSPI_INTENSET_DMADONE_Min (0x0UL)

#define	QSPI_INTENSET_DMADONE_Max (0x1UL)

#define	QSPI_INTENSET_DMADONE_Set (0x1UL)

#define	QSPI_INTENSET_DMADONE_Disabled (0x0UL)

#define	QSPI_INTENSET_DMADONE_Enabled (0x1UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos (10UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Set (0x1UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Disabled (0x0UL)

#define	QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Enabled (0x1UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Pos (11UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Msk (0x1UL << QSPI_INTENSET_DMAINTERNALBUSERROR_Pos)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Min (0x0UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Max (0x1UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Set (0x1UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Disabled (0x0UL)

#define	QSPI_INTENSET_DMAINTERNALBUSERROR_Enabled (0x1UL)

#define	QSPI_INTENSET_DMAABORTED_Pos (12UL)

#define	QSPI_INTENSET_DMAABORTED_Msk (0x1UL << QSPI_INTENSET_DMAABORTED_Pos)

#define	QSPI_INTENSET_DMAABORTED_Min (0x0UL)

#define	QSPI_INTENSET_DMAABORTED_Max (0x1UL)

#define	QSPI_INTENSET_DMAABORTED_Set (0x1UL)

#define	QSPI_INTENSET_DMAABORTED_Disabled (0x0UL)

#define	QSPI_INTENSET_DMAABORTED_Enabled (0x1UL)

#define	QSPI_INTENSET_IDLE_Pos (13UL)

#define	QSPI_INTENSET_IDLE_Msk (0x1UL << QSPI_INTENSET_IDLE_Pos)

#define	QSPI_INTENSET_IDLE_Min (0x0UL)

#define	QSPI_INTENSET_IDLE_Max (0x1UL)

#define	QSPI_INTENSET_IDLE_Set (0x1UL)

#define	QSPI_INTENSET_IDLE_Disabled (0x0UL)

#define	QSPI_INTENSET_IDLE_Enabled (0x1UL)

#define	QSPI_INTENCLR_ResetValue (0x00000000UL)

#define	QSPI_INTENCLR_CORE_Pos (0UL)

#define	QSPI_INTENCLR_CORE_Msk (0x1UL << QSPI_INTENCLR_CORE_Pos)

#define	QSPI_INTENCLR_CORE_Min (0x0UL)

#define	QSPI_INTENCLR_CORE_Max (0x1UL)

#define	QSPI_INTENCLR_CORE_Clear (0x1UL)

#define	QSPI_INTENCLR_CORE_Disabled (0x0UL)

#define	QSPI_INTENCLR_CORE_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONELIST_Pos (1UL)

#define	QSPI_INTENCLR_DMADONELIST_Msk (0x1UL << QSPI_INTENCLR_DMADONELIST_Pos)

#define	QSPI_INTENCLR_DMADONELIST_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONELIST_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONELIST_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONELIST_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONELIST_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Pos (2UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Msk (0x1UL << QSPI_INTENCLR_DMADONELISTPART_Pos)

#define	QSPI_INTENCLR_DMADONELISTPART_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONELISTPART_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Pos (3UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Msk (0x1UL << QSPI_INTENCLR_DMADONESELECTJOB_Pos)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONESELECTJOB_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONEDATA_Pos (4UL)

#define	QSPI_INTENCLR_DMADONEDATA_Msk (0x1UL << QSPI_INTENCLR_DMADONEDATA_Pos)

#define	QSPI_INTENCLR_DMADONEDATA_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONEDATA_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONEDATA_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONEDATA_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONEDATA_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONEJOB_Pos (5UL)

#define	QSPI_INTENCLR_DMADONEJOB_Msk (0x1UL << QSPI_INTENCLR_DMADONEJOB_Pos)

#define	QSPI_INTENCLR_DMADONEJOB_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONEJOB_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONEJOB_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONEJOB_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONEJOB_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMAERROR_Pos (6UL)

#define	QSPI_INTENCLR_DMAERROR_Msk (0x1UL << QSPI_INTENCLR_DMAERROR_Pos)

#define	QSPI_INTENCLR_DMAERROR_Min (0x0UL)

#define	QSPI_INTENCLR_DMAERROR_Max (0x1UL)

#define	QSPI_INTENCLR_DMAERROR_Clear (0x1UL)

#define	QSPI_INTENCLR_DMAERROR_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMAERROR_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMAPAUSED_Pos (7UL)

#define	QSPI_INTENCLR_DMAPAUSED_Msk (0x1UL << QSPI_INTENCLR_DMAPAUSED_Pos)

#define	QSPI_INTENCLR_DMAPAUSED_Min (0x0UL)

#define	QSPI_INTENCLR_DMAPAUSED_Max (0x1UL)

#define	QSPI_INTENCLR_DMAPAUSED_Clear (0x1UL)

#define	QSPI_INTENCLR_DMAPAUSED_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMAPAUSED_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMARESET_Pos (8UL)

#define	QSPI_INTENCLR_DMARESET_Msk (0x1UL << QSPI_INTENCLR_DMARESET_Pos)

#define	QSPI_INTENCLR_DMARESET_Min (0x0UL)

#define	QSPI_INTENCLR_DMARESET_Max (0x1UL)

#define	QSPI_INTENCLR_DMARESET_Clear (0x1UL)

#define	QSPI_INTENCLR_DMARESET_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMARESET_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMADONE_Pos (9UL)

#define	QSPI_INTENCLR_DMADONE_Msk (0x1UL << QSPI_INTENCLR_DMADONE_Pos)

#define	QSPI_INTENCLR_DMADONE_Min (0x0UL)

#define	QSPI_INTENCLR_DMADONE_Max (0x1UL)

#define	QSPI_INTENCLR_DMADONE_Clear (0x1UL)

#define	QSPI_INTENCLR_DMADONE_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMADONE_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos (10UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Clear (0x1UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos (11UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Msk (0x1UL << QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Min (0x0UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Max (0x1UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Clear (0x1UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMAINTERNALBUSERROR_Enabled (0x1UL)

#define	QSPI_INTENCLR_DMAABORTED_Pos (12UL)

#define	QSPI_INTENCLR_DMAABORTED_Msk (0x1UL << QSPI_INTENCLR_DMAABORTED_Pos)

#define	QSPI_INTENCLR_DMAABORTED_Min (0x0UL)

#define	QSPI_INTENCLR_DMAABORTED_Max (0x1UL)

#define	QSPI_INTENCLR_DMAABORTED_Clear (0x1UL)

#define	QSPI_INTENCLR_DMAABORTED_Disabled (0x0UL)

#define	QSPI_INTENCLR_DMAABORTED_Enabled (0x1UL)

#define	QSPI_INTENCLR_IDLE_Pos (13UL)

#define	QSPI_INTENCLR_IDLE_Msk (0x1UL << QSPI_INTENCLR_IDLE_Pos)

#define	QSPI_INTENCLR_IDLE_Min (0x0UL)

#define	QSPI_INTENCLR_IDLE_Max (0x1UL)

#define	QSPI_INTENCLR_IDLE_Clear (0x1UL)

#define	QSPI_INTENCLR_IDLE_Disabled (0x0UL)

#define	QSPI_INTENCLR_IDLE_Enabled (0x1UL)

#define	QSPI_INTPEND_ResetValue (0x00000000UL)

#define	QSPI_INTPEND_CORE_Pos (0UL)

#define	QSPI_INTPEND_CORE_Msk (0x1UL << QSPI_INTPEND_CORE_Pos)

#define	QSPI_INTPEND_CORE_Min (0x0UL)

#define	QSPI_INTPEND_CORE_Max (0x1UL)

#define	QSPI_INTPEND_CORE_NotPending (0x0UL)

#define	QSPI_INTPEND_CORE_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONELIST_Pos (1UL)

#define	QSPI_INTPEND_DMADONELIST_Msk (0x1UL << QSPI_INTPEND_DMADONELIST_Pos)

#define	QSPI_INTPEND_DMADONELIST_Min (0x0UL)

#define	QSPI_INTPEND_DMADONELIST_Max (0x1UL)

#define	QSPI_INTPEND_DMADONELIST_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONELIST_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONELISTPART_Pos (2UL)

#define	QSPI_INTPEND_DMADONELISTPART_Msk (0x1UL << QSPI_INTPEND_DMADONELISTPART_Pos)

#define	QSPI_INTPEND_DMADONELISTPART_Min (0x0UL)

#define	QSPI_INTPEND_DMADONELISTPART_Max (0x1UL)

#define	QSPI_INTPEND_DMADONELISTPART_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONELISTPART_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONESELECTJOB_Pos (3UL)

#define	QSPI_INTPEND_DMADONESELECTJOB_Msk (0x1UL << QSPI_INTPEND_DMADONESELECTJOB_Pos)

#define	QSPI_INTPEND_DMADONESELECTJOB_Min (0x0UL)

#define	QSPI_INTPEND_DMADONESELECTJOB_Max (0x1UL)

#define	QSPI_INTPEND_DMADONESELECTJOB_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONESELECTJOB_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONEDATA_Pos (4UL)

#define	QSPI_INTPEND_DMADONEDATA_Msk (0x1UL << QSPI_INTPEND_DMADONEDATA_Pos)

#define	QSPI_INTPEND_DMADONEDATA_Min (0x0UL)

#define	QSPI_INTPEND_DMADONEDATA_Max (0x1UL)

#define	QSPI_INTPEND_DMADONEDATA_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONEDATA_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONEJOB_Pos (5UL)

#define	QSPI_INTPEND_DMADONEJOB_Msk (0x1UL << QSPI_INTPEND_DMADONEJOB_Pos)

#define	QSPI_INTPEND_DMADONEJOB_Min (0x0UL)

#define	QSPI_INTPEND_DMADONEJOB_Max (0x1UL)

#define	QSPI_INTPEND_DMADONEJOB_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONEJOB_Pending (0x1UL)

#define	QSPI_INTPEND_DMAERROR_Pos (6UL)

#define	QSPI_INTPEND_DMAERROR_Msk (0x1UL << QSPI_INTPEND_DMAERROR_Pos)

#define	QSPI_INTPEND_DMAERROR_Min (0x0UL)

#define	QSPI_INTPEND_DMAERROR_Max (0x1UL)

#define	QSPI_INTPEND_DMAERROR_NotPending (0x0UL)

#define	QSPI_INTPEND_DMAERROR_Pending (0x1UL)

#define	QSPI_INTPEND_DMAPAUSED_Pos (7UL)

#define	QSPI_INTPEND_DMAPAUSED_Msk (0x1UL << QSPI_INTPEND_DMAPAUSED_Pos)

#define	QSPI_INTPEND_DMAPAUSED_Min (0x0UL)

#define	QSPI_INTPEND_DMAPAUSED_Max (0x1UL)

#define	QSPI_INTPEND_DMAPAUSED_NotPending (0x0UL)

#define	QSPI_INTPEND_DMAPAUSED_Pending (0x1UL)

#define	QSPI_INTPEND_DMARESET_Pos (8UL)

#define	QSPI_INTPEND_DMARESET_Msk (0x1UL << QSPI_INTPEND_DMARESET_Pos)

#define	QSPI_INTPEND_DMARESET_Min (0x0UL)

#define	QSPI_INTPEND_DMARESET_Max (0x1UL)

#define	QSPI_INTPEND_DMARESET_NotPending (0x0UL)

#define	QSPI_INTPEND_DMARESET_Pending (0x1UL)

#define	QSPI_INTPEND_DMADONE_Pos (9UL)

#define	QSPI_INTPEND_DMADONE_Msk (0x1UL << QSPI_INTPEND_DMADONE_Pos)

#define	QSPI_INTPEND_DMADONE_Min (0x0UL)

#define	QSPI_INTPEND_DMADONE_Max (0x1UL)

#define	QSPI_INTPEND_DMADONE_NotPending (0x0UL)

#define	QSPI_INTPEND_DMADONE_Pending (0x1UL)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos (10UL)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Msk (0x1UL << QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Min (0x0UL)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Max (0x1UL)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_NotPending (0x0UL)

#define	QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pending (0x1UL)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_Pos (11UL)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_Msk (0x1UL << QSPI_INTPEND_DMAINTERNALBUSERROR_Pos)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_Min (0x0UL)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_Max (0x1UL)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_NotPending (0x0UL)

#define	QSPI_INTPEND_DMAINTERNALBUSERROR_Pending (0x1UL)

#define	QSPI_INTPEND_DMAABORTED_Pos (12UL)

#define	QSPI_INTPEND_DMAABORTED_Msk (0x1UL << QSPI_INTPEND_DMAABORTED_Pos)

#define	QSPI_INTPEND_DMAABORTED_Min (0x0UL)

#define	QSPI_INTPEND_DMAABORTED_Max (0x1UL)

#define	QSPI_INTPEND_DMAABORTED_NotPending (0x0UL)

#define	QSPI_INTPEND_DMAABORTED_Pending (0x1UL)

#define	QSPI_INTPEND_IDLE_Pos (13UL)

#define	QSPI_INTPEND_IDLE_Msk (0x1UL << QSPI_INTPEND_IDLE_Pos)

#define	QSPI_INTPEND_IDLE_Min (0x0UL)

#define	QSPI_INTPEND_IDLE_Max (0x1UL)

#define	QSPI_INTPEND_IDLE_NotPending (0x0UL)

#define	QSPI_INTPEND_IDLE_Pending (0x1UL)

#define	QSPI_ENABLE_ResetValue (0x00000000UL)

#define	QSPI_ENABLE_ENABLE_Pos (0UL)

#define	QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos)

Data Structures

Macros