doxygen/html/nrf__sp__qspi_8h_source.html

/*

 * Copyright (c) 2025 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

 */


#ifndef NRF_SP_QSPI_H__

#define NRF_SP_QSPI_H__


#include "nrfx.h"             // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc.

/* ===========================================================================================================================

 * ================                                           QSPI                                           ================

 * ===========================================================================================================================*/


#if !defined(__ASSEMBLER__) \

    && !defined(__ASSEMBLY__)


/* =========================================== Struct QSPI_EVENTS_DMA_EVENTS_DONE ============================================ */


typedef struct

{

    __IOM uint32_t LIST;

    __IOM uint32_t LISTPART;

    __IOM uint32_t SELECTJOB;

    __IOM uint32_t DATA;

    __IOM uint32_t JOB;

} NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type;


/* QSPI_EVENTS_DMA_EVENTS_DONE_LIST: Descriptor list is complete. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_ResetValue \

    (0x00000000UL)


/* LIST @Bit 0 : Descriptor list is complete. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Msk \

    (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Pos)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LIST_LIST_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART: Descriptor list is partially complete. Threshold in CONFIG.LISTPARTTHRESH register has

 *                                        been passed. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_ResetValue \

    (0x00000000UL)


/* LISTPART @Bit 0 : Descriptor list is partially complete. Threshold in CONFIG.LISTPARTTHRESH register has been passed. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Msk \

    (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Pos)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_LISTPART_LISTPART_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB: Selected job is completed. Selection is done via CONFIG.SELECTJOBENABLE. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_ResetValue \

    (0x00000000UL)


/* SELECTJOB @Bit 0 : Selected job is completed. Selection is done via CONFIG.SELECTJOBENABLE. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Msk \

    (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Pos)


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_SELECTJOB_SELECTJOB_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_EVENTS_DONE_DATA: A job has been completed, i.e. the job's data has been completely transferred either to AXI

 *                                    or DMA bus, depending on direction. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_ResetValue \

    (0x00000000UL)


/* DATA @Bit 0 : A job has been completed, i.e. the job's data has been completely transferred either to AXI or DMA bus,

 *               depending on direction. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Msk \

    (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Pos)


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_DATA_DATA_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_EVENTS_DONE_JOB: A job has been fetched from the joblist. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_ResetValue \

    (0x00000000UL)


/* JOB @Bit 0 : A job has been fetched from the joblist. */


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Msk \

    (0x1UL << QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Pos)


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_EVENTS_DONE_JOB_JOB_Generated \

    (0x1UL)


/* ================================================= Struct QSPI_EVENTS_DMA ================================================== */


typedef struct

{

    __IOM NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type

                   EVENTS_DONE;

    __IOM uint32_t ERROR;

    __IOM uint32_t PAUSED;

    __IOM uint32_t RESET;

    __IOM uint32_t DONE;

    __IOM uint32_t TXUNEXPECTEDIDLE;

    __IOM uint32_t INTERNALBUSERROR;

    __IOM uint32_t ABORTED;

} NRF_QSPI_EVENTS_DMA_Type;


/* QSPI_EVENTS_DMA_ERROR: AXI bus error received. */


#define QSPI_EVENTS_DMA_ERROR_ResetValue \

    (0x00000000UL)


/* ERROR @Bit 0 : AXI bus error received. */


#define QSPI_EVENTS_DMA_ERROR_ERROR_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_ERROR_ERROR_Msk \

    (0x1UL << QSPI_EVENTS_DMA_ERROR_ERROR_Pos)


#define QSPI_EVENTS_DMA_ERROR_ERROR_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_ERROR_ERROR_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_ERROR_ERROR_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_ERROR_ERROR_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_PAUSED: DMA paused with task TASKS_PAUSE. */


#define QSPI_EVENTS_DMA_PAUSED_ResetValue \

    (0x00000000UL)


/* PAUSED @Bit 0 : DMA paused with task TASKS_PAUSE. */


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_Msk \

    (0x1UL << QSPI_EVENTS_DMA_PAUSED_PAUSED_Pos)


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_PAUSED_PAUSED_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_RESET: DMA reset with task TASKS_RESET. */


#define QSPI_EVENTS_DMA_RESET_ResetValue \

    (0x00000000UL)


/* RESET @Bit 0 : DMA reset with task TASKS_RESET. */


#define QSPI_EVENTS_DMA_RESET_RESET_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_RESET_RESET_Msk \

    (0x1UL << QSPI_EVENTS_DMA_RESET_RESET_Pos)


#define QSPI_EVENTS_DMA_RESET_RESET_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_RESET_RESET_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_RESET_RESET_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_RESET_RESET_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_DONE: DMA transfer done */


#define QSPI_EVENTS_DMA_DONE_ResetValue \

    (0x00000000UL)


/* DONE @Bit 0 : DMA transfer done */

#define QSPI_EVENTS_DMA_DONE_DONE_Pos (0UL)


#define QSPI_EVENTS_DMA_DONE_DONE_Msk \

    (0x1UL << QSPI_EVENTS_DMA_DONE_DONE_Pos)


#define QSPI_EVENTS_DMA_DONE_DONE_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_DONE_DONE_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_DONE_DONE_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_DONE_DONE_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE: The QSPI core has gone into idle state at an unexpected time, this can happen if the TX

 *                                    buffer underflows, this event is followed by either DONE or ABORTED event. Triggered by

 *                                    the CORE being idle while we still have data to transfer to the CORE. */


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_ResetValue \

    (0x00000000UL)


/* TXUNEXPECTEDIDLE @Bit 0 : The QSPI core has gone into idle state at an unexpected time, this can happen if the TX buffer

 *                           underflows, this event is followed by either DONE or ABORTED event. Triggered by the CORE being

 *                           idle while we still have data to transfer to the CORE. */


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Pos)


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_TXUNEXPECTEDIDLE_TXUNEXPECTEDIDLE_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_INTERNALBUSERROR: An error occured during the transfer of data internally in the QSPI, followed by either

 *                                    DONE or ABORTED event. This event is generated on an AHB error response on the easyDMA

 *                                    towards the QSPI CORE. The BUSERROR address is not given in a register since the target

 *                                    register address is fixed. */


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_ResetValue \

    (0x00000000UL)


/* INTERNALBUSERROR @Bit 0 : An error occured during the transfer of data internally in the QSPI, followed by either DONE or

 *                           ABORTED event. This event is generated on an AHB error response on the easyDMA towards the QSPI

 *                           CORE. The BUSERROR address is not given in a register since the target register address is fixed. */


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Msk \

    (0x1UL << QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Pos)


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_INTERNALBUSERROR_INTERNALBUSERROR_Generated \

    (0x1UL)


/* QSPI_EVENTS_DMA_ABORTED: The QSPI DMA has aborted due to an error given in a separate event, and has attempted to complete

 *                           any ongoing transactions, and stopped. The QSPI DMA is ready for a new transaction. */


#define QSPI_EVENTS_DMA_ABORTED_ResetValue \

    (0x00000000UL)


/* ABORTED @Bit 0 : The QSPI DMA has aborted due to an error given in a separate event, and has attempted to complete any

 *                  ongoing transactions, and stopped. The QSPI DMA is ready for a new transaction. */


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_Pos \

    (0UL)


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_Msk \

    (0x1UL << QSPI_EVENTS_DMA_ABORTED_ABORTED_Pos)


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_Min \

    (0x0UL)


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_Max \

    (0x1UL)


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_DMA_ABORTED_ABORTED_Generated \

    (0x1UL)


/* =================================================== Struct QSPI_CONFIG ==================================================== */


typedef struct

{

    __IOM uint32_t TXBURSTLENGTH;

    __IOM uint32_t RXBURSTLENGTH;

    __IOM uint32_t RXTRANSFERLENGTH;

    __IOM uint32_t STOPON;

    __IOM uint32_t AXIMODE;

} NRF_QSPI_CONFIG_Type;


/* QSPI_CONFIG_TXBURSTLENGTH: Transmit burst length */


#define QSPI_CONFIG_TXBURSTLENGTH_ResetValue \

    (0x00000008UL)


/* AMOUNT @Bits 0..4 : Number of buffer lines */


#define QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Pos \

    (0UL)


#define QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Msk \

    (0x1FUL << QSPI_CONFIG_TXBURSTLENGTH_AMOUNT_Pos)


/* QSPI_CONFIG_RXBURSTLENGTH: Receive burst length */


#define QSPI_CONFIG_RXBURSTLENGTH_ResetValue \

    (0x00000008UL)


/* AMOUNT @Bits 0..4 : Number of buffer lines */


#define QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Pos \

    (0UL)


#define QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Msk \

    (0x1FUL << QSPI_CONFIG_RXBURSTLENGTH_AMOUNT_Pos)


/* QSPI_CONFIG_RXTRANSFERLENGTH: Receive transfer full length */


#define QSPI_CONFIG_RXTRANSFERLENGTH_ResetValue \

    (0x00000010UL)


/* AMOUNT @Bits 0..17 : Number of buffer lines */


#define QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Pos \

    (0UL)


#define QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Msk \

    (0x3FFFFUL << QSPI_CONFIG_RXTRANSFERLENGTH_AMOUNT_Pos)


/* QSPI_CONFIG_STOPON: Stop the DMA if the CORE goes into any of the enabled states. */


#define QSPI_CONFIG_STOPON_ResetValue \

    (0x00000003UL)


/* TXUNEXPECTEDIDLE @Bit 0 : The CORE will go into idle if the CORE buffer is emptied, if the DMA still has data to transfer the

 *                           CORE is not expected to go into idle state. This constitutes a buffer underflow. The CORE migth

 *                           also go into idle if an error occurs. */


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Pos \

    (0UL)


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Pos)


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Disabled \

    (0x0UL)


#define QSPI_CONFIG_STOPON_TXUNEXPECTEDIDLE_Enabled \

    (0x1UL)


/* RXOVERFLOW @Bit 1 : This condition occurrs if the DMA attempts to write to the RX buffer in the CORE, but the buffer is full.

 *                     When this bit is enabled the DMA will stop when the CORE buffer experiences a rx buffer overflow */


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Pos \

    (1UL)


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Msk \

    (0x1UL << QSPI_CONFIG_STOPON_RXOVERFLOW_Pos)


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Min \

    (0x0UL)


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Max \

    (0x1UL)


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Disabled \

    (0x0UL)


#define QSPI_CONFIG_STOPON_RXOVERFLOW_Enabled \

    (0x1UL)


/* INTERNALBUSERROR @Bit 2 : Terminate the transaction if a INTERNALBUSERROR event is detected. */


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Pos \

    (2UL)


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Msk \

    (0x1UL << QSPI_CONFIG_STOPON_INTERNALBUSERROR_Pos)


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Disabled \

    (0x0UL)


#define QSPI_CONFIG_STOPON_INTERNALBUSERROR_Enabled \

    (0x1UL)


/* DMABUSERROR @Bit 3 : Terminate the transaction if a DMA.ERROR event is detected. */


#define QSPI_CONFIG_STOPON_DMABUSERROR_Pos \

    (3UL)


#define QSPI_CONFIG_STOPON_DMABUSERROR_Msk \

    (0x1UL << QSPI_CONFIG_STOPON_DMABUSERROR_Pos)


#define QSPI_CONFIG_STOPON_DMABUSERROR_Min \

    (0x0UL)


#define QSPI_CONFIG_STOPON_DMABUSERROR_Max \

    (0x1UL)


#define QSPI_CONFIG_STOPON_DMABUSERROR_Disabled \

    (0x0UL)


#define QSPI_CONFIG_STOPON_DMABUSERROR_Enabled \

    (0x1UL)


/* QSPI_CONFIG_AXIMODE: Determines if AXI-lite or full AXI is used. */


#define QSPI_CONFIG_AXIMODE_ResetValue \

    (0x00000000UL)


/* AXIMODE @Bit 4 : Type of AXI access. */


#define QSPI_CONFIG_AXIMODE_AXIMODE_Pos \

    (4UL)


#define QSPI_CONFIG_AXIMODE_AXIMODE_Msk \

    (0x1UL << QSPI_CONFIG_AXIMODE_AXIMODE_Pos)


#define QSPI_CONFIG_AXIMODE_AXIMODE_Min \

    (0x0UL)


#define QSPI_CONFIG_AXIMODE_AXIMODE_Max \

    (0x1UL)


#define QSPI_CONFIG_AXIMODE_AXIMODE_Lite \

    (0x0UL)


#define QSPI_CONFIG_AXIMODE_AXIMODE_Full \

    (0x1UL)


/* MODE @Bit 5 : (unspecified) */

#define QSPI_CONFIG_AXIMODE_MODE_Pos (5UL)


#define QSPI_CONFIG_AXIMODE_MODE_Msk \

    (0x1UL << QSPI_CONFIG_AXIMODE_MODE_Pos)


/* =================================================== Struct QSPI_FORMAT ==================================================== */


typedef struct

{

    __IOM uint32_t DFS;

    __IOM uint32_t BPP;

    __IOM uint32_t PIXELS;

    __IOM uint32_t CILEN;

    __IOM uint32_t BITORDER;

} NRF_QSPI_FORMAT_Type;


/* QSPI_FORMAT_DFS: Data frame size */


#define QSPI_FORMAT_DFS_ResetValue \

    (0x00000000UL)


/* DFS @Bits 0..5 : (unspecified) */

#define QSPI_FORMAT_DFS_DFS_Pos (0UL)


#define QSPI_FORMAT_DFS_DFS_Msk \

    (0x3FUL << QSPI_FORMAT_DFS_DFS_Pos)


/* QSPI_FORMAT_BPP: Bits per pixel */


#define QSPI_FORMAT_BPP_ResetValue \

    (0x00000000UL)


/* BPP @Bits 0..5 : (unspecified) */

#define QSPI_FORMAT_BPP_BPP_Pos (0UL)


#define QSPI_FORMAT_BPP_BPP_Msk \

    (0x3FUL << QSPI_FORMAT_BPP_BPP_Pos)


#define QSPI_FORMAT_BPP_BPP_Min (0x0UL)

#define QSPI_FORMAT_BPP_BPP_Max (0x10UL)

#define QSPI_FORMAT_BPP_BPP_0   (0x00UL)

#define QSPI_FORMAT_BPP_BPP_4   (0x04UL)

#define QSPI_FORMAT_BPP_BPP_8   (0x08UL)

#define QSPI_FORMAT_BPP_BPP_16  (0x10UL)


/* QSPI_FORMAT_PIXELS: Number of pixels following the command */


#define QSPI_FORMAT_PIXELS_ResetValue \

    (0x00000000UL)


/* PIXELS @Bits 0..17 : Number of pixels */

#define QSPI_FORMAT_PIXELS_PIXELS_Pos (0UL)


#define QSPI_FORMAT_PIXELS_PIXELS_Msk \

    (0x3FFFFUL << QSPI_FORMAT_PIXELS_PIXELS_Pos)


/* QSPI_FORMAT_CILEN: Command/Instruction length */


#define QSPI_FORMAT_CILEN_ResetValue \

    (0x00000000UL)


/* CILEN @Bits 0..1 : Number of words */

#define QSPI_FORMAT_CILEN_CILEN_Pos (0UL)


#define QSPI_FORMAT_CILEN_CILEN_Msk \

    (0x3UL << QSPI_FORMAT_CILEN_CILEN_Pos)


/* QSPI_FORMAT_BITORDER: Bit Order */


#define QSPI_FORMAT_BITORDER_ResetValue \

    (0x00000000UL)


#define QSPI_FORMAT_BITORDER_COMMAND_Pos (0UL)


#define QSPI_FORMAT_BITORDER_COMMAND_Msk \

    (0x1UL << QSPI_FORMAT_BITORDER_COMMAND_Pos)


#define QSPI_FORMAT_BITORDER_DATA_Pos    (1UL)


#define QSPI_FORMAT_BITORDER_DATA_Msk \

    (0x1UL << QSPI_FORMAT_BITORDER_DATA_Pos)


/* ================================================= Struct QSPI_DMA_STATUS ================================================== */


typedef struct

{

    __IM uint32_t BYTECOUNT;

    __IM uint32_t ATTRIBUTE;

    __IM uint32_t ADDRESS;

    __IM uint32_t JOBCOUNT;

    __IM uint32_t BUSERROR;

    __IM uint32_t FIFO;

    __IM uint32_t ACTIVE;

} NRF_QSPI_DMA_STATUS_Type;


/* QSPI_DMA_STATUS_BYTECOUNT: Number of bytes sent or received during processing of current descriptor list */


#define QSPI_DMA_STATUS_BYTECOUNT_ResetValue \

    (0x00000000UL)


/* BYTECOUNT @Bits 0..31 : Number of bytes sent or received during processing of current descriptor list */


#define QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Pos \

    (0UL)


#define QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Msk \

    (0xFFFFFFFFUL << QSPI_DMA_STATUS_BYTECOUNT_BYTECOUNT_Pos)


/* QSPI_DMA_STATUS_ATTRIBUTE: Latest job attribute being processed. */


#define QSPI_DMA_STATUS_ATTRIBUTE_ResetValue \

    (0x00000000UL)


/* ATTRIBUTE @Bits 0..5 : Latest job attribute being processed. */


#define QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Pos \

    (0UL)


#define QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Msk \

    (0x3FUL << QSPI_DMA_STATUS_ATTRIBUTE_ATTRIBUTE_Pos)


/* QSPI_DMA_STATUS_ADDRESS: Latest address being accessed. */


#define QSPI_DMA_STATUS_ADDRESS_ResetValue \

    (0x00000000UL)


/* ADDRESS @Bits 0..31 : Latest address being accessed. */


#define QSPI_DMA_STATUS_ADDRESS_ADDRESS_Pos \

    (0UL)


#define QSPI_DMA_STATUS_ADDRESS_ADDRESS_Msk \

    (0xFFFFFFFFUL << QSPI_DMA_STATUS_ADDRESS_ADDRESS_Pos)


/* QSPI_DMA_STATUS_JOBCOUNT: Number of completed jobs in current descriptor list. */


#define QSPI_DMA_STATUS_JOBCOUNT_ResetValue \

    (0x00000000UL)


/* JOBCOUNT @Bits 0..31 : Number of completed jobs in current descriptor list. */


#define QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Pos \

    (0UL)


#define QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Msk \

    (0xFFFFFFFFUL << QSPI_DMA_STATUS_JOBCOUNT_JOBCOUNT_Pos)


/* QSPI_DMA_STATUS_BUSERROR: AXI bus error status. */


#define QSPI_DMA_STATUS_BUSERROR_ResetValue \

    (0x00000000UL)


/* BUSERROR @Bits 0..2 : AXI bus error type */


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_Pos \

    (0UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_Msk \

    (0x7UL << QSPI_DMA_STATUS_BUSERROR_BUSERROR_Pos)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_Min \

    (0x0UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_Max \

    (0x4UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_NoError \

    (0x0UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_ReadError \

    (0x1UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_ReadDecodeError \

    (0x2UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_WriteError \

    (0x3UL)


#define QSPI_DMA_STATUS_BUSERROR_BUSERROR_WriteDecodeError \

    (0x4UL)


/* QSPI_DMA_STATUS_FIFO: Data fifo status. */


#define QSPI_DMA_STATUS_FIFO_ResetValue \

    (0x00000000UL)


/* RXFIFO @Bits 0..1 : Memory-to-Peripheral direction data fifo status */


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Pos \

    (0UL)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Msk \

    (0x3UL << QSPI_DMA_STATUS_FIFO_RXFIFO_Pos)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Min \

    (0x0UL)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Max \

    (0x2UL)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Empty \

    (0x0UL)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_NotEmpty \

    (0x1UL)


#define QSPI_DMA_STATUS_FIFO_RXFIFO_Full \

    (0x2UL)


/* TXFIFO @Bits 2..3 : Peripheral-to-Memory direction data fifo status */


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Pos \

    (2UL)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Msk \

    (0x3UL << QSPI_DMA_STATUS_FIFO_TXFIFO_Pos)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Min \

    (0x0UL)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Max \

    (0x2UL)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Empty \

    (0x0UL)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_NotEmpty \

    (0x1UL)


#define QSPI_DMA_STATUS_FIFO_TXFIFO_Full \

    (0x2UL)


/* QSPI_DMA_STATUS_ACTIVE: DMA activity state. */


#define QSPI_DMA_STATUS_ACTIVE_ResetValue \

    (0x00000000UL)


/* ACTIVE @Bit 0 : DMA activity state. */


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Pos \

    (0UL)


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Msk \

    (0x1UL << QSPI_DMA_STATUS_ACTIVE_ACTIVE_Pos)


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Min \

    (0x0UL)


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Max \

    (0x1UL)


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Idle \

    (0x0UL)


#define QSPI_DMA_STATUS_ACTIVE_ACTIVE_Active \

    (0x1UL)


/* ================================================= Struct QSPI_DMA_CONFIG ================================================== */


typedef struct

{

    __IOM uint32_t BUFFERFILL;

    __IOM uint32_t LISTPTR;

    __IOM uint32_t LISTPARTTHRESH;

} NRF_QSPI_DMA_CONFIG_Type;


/* QSPI_DMA_CONFIG_BUFFERFILL: Data to be used when data is sent with BufferFill attribute */


#define QSPI_DMA_CONFIG_BUFFERFILL_ResetValue \

    (0x00000000UL)


/* BUFFERFILL @Bits 0..7 : Data to be used when data is sent with BufferFill attribute */


#define QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Pos \

    (0UL)


#define QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Msk \

    (0xFFUL << QSPI_DMA_CONFIG_BUFFERFILL_BUFFERFILL_Pos)


/* QSPI_DMA_CONFIG_LISTPTR: Start address of descriptor list */


#define QSPI_DMA_CONFIG_LISTPTR_ResetValue \

    (0x00000000UL)


/* LISTPTR @Bits 0..31 : Start address of descriptor list */


#define QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Pos \

    (0UL)


#define QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Msk \

    (0xFFFFFFFFUL << QSPI_DMA_CONFIG_LISTPTR_LISTPTR_Pos)


/* QSPI_DMA_CONFIG_LISTPARTTHRESH: Threshold value for generating event EVENTS_DONE.PARTLIST when descriptor list is partially

 *                                  completed. Value is number of jobs. */


#define QSPI_DMA_CONFIG_LISTPARTTHRESH_ResetValue \

    (0x00000000UL)


/* LISTPARTTHRESH @Bits 0..15 : Threshold value. */


#define QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Pos \

    (0UL)


#define QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Msk \

    (0xFFFFUL << QSPI_DMA_CONFIG_LISTPARTTHRESH_LISTPARTTHRESH_Pos)


/* ===================================================== Struct QSPI_DMA ===================================================== */


typedef struct

{

    __IOM NRF_QSPI_DMA_STATUS_Type STATUS;

    __IOM NRF_QSPI_DMA_CONFIG_Type CONFIG;

} NRF_QSPI_DMA_Type;


/* ================================================== Struct QSPI_CORE_CORE ================================================== */


typedef struct

{

    __IOM uint32_t CTRLR0;

    __IOM uint32_t CTRLR1;

    __IOM uint32_t SQSPIENR;

    __IOM uint32_t MWCR;

    __IOM uint32_t SER;

    __IOM uint32_t BAUDR;

    __IOM uint32_t TXFTLR;

    __IOM uint32_t RXFTLR;

    __IOM uint32_t TXFLR;

    __IOM uint32_t RXFLR;

    __IOM uint32_t SR;

    __IOM uint32_t IMR;

    __IOM uint32_t ISR;

    __IOM uint32_t RISR;

    __IOM uint32_t TXEICR;

    __IOM uint32_t RXOICR;

    __IOM uint32_t RXUICR;

    __IOM uint32_t MSTICR;

    __IOM uint32_t ICR;

    __IOM uint32_t DMACR;

    __IOM uint32_t DMATDLR;

    __IOM uint32_t DMARDLR;

    __IOM uint32_t IDR;

    __IOM uint32_t SQSPICVERSIONID;

    __IOM uint32_t DR[36];

    __IOM uint32_t RXSAMPLEDELAY;

    __IOM uint32_t SPICTRLR0;

    __IOM uint32_t SPICTRLR1;

    __IOM uint32_t SPITECR;

} NRF_QSPI_CORE_CORE_Type;


/* QSPI_CORE_CORE_CTRLR0: Control Register 0 */


#define QSPI_CORE_CORE_CTRLR0_ResetValue \

    (0x00000007UL)


/* DFS @Bits 0..4 : Data Frame Size. */

#define QSPI_CORE_CORE_CTRLR0_DFS_Pos (0UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_Msk \

    (0x1FUL << QSPI_CORE_CORE_CTRLR0_DFS_Pos)


#define QSPI_CORE_CORE_CTRLR0_DFS_Min \

    (0x3UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_Max \

    (0x1FUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS04BIT \

    (0x03UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS05BIT \

    (0x04UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS06BIT \

    (0x05UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS07BIT \

    (0x06UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS08BIT \

    (0x07UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS09BIT \

    (0x08UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS10BIT \

    (0x09UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS11BIT \

    (0x0AUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS12BIT \

    (0x0BUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS13BIT \

    (0x0CUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS14BIT \

    (0x0DUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS15BIT \

    (0x0EUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS16BIT \

    (0x0FUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS17BIT \

    (0x10UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS18BIT \

    (0x11UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS19BIT \

    (0x12UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS20BIT \

    (0x13UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS21BIT \

    (0x14UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS22BIT \

    (0x15UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS23BIT \

    (0x16UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS24BIT \

    (0x17UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS25BIT \

    (0x18UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS26BIT \

    (0x19UL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS27BIT \

    (0x1AUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS28BIT \

    (0x1BUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS29BIT \

    (0x1CUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS30BIT \

    (0x1DUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS31BIT \

    (0x1EUL)


#define QSPI_CORE_CORE_CTRLR0_DFS_DFS32BIT \

    (0x1FUL)


/* RSVDCTRLR05 @Bit 5 : (unspecified) */


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Pos \

    (5UL)


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR05_Pos)


/* FRF @Bits 6..7 : Frame Format. */

#define QSPI_CORE_CORE_CTRLR0_FRF_Pos (6UL)


#define QSPI_CORE_CORE_CTRLR0_FRF_Msk \

    (0x3UL << QSPI_CORE_CORE_CTRLR0_FRF_Pos)


#define QSPI_CORE_CORE_CTRLR0_FRF_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_FRF_Max \

    (0x2UL)


#define QSPI_CORE_CORE_CTRLR0_FRF_SPI \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_FRF_SSP \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_FRF_MICROWIRE \

    (0x2UL)


/* SCPH @Bit 8 : Serial Clock Phase. */


#define QSPI_CORE_CORE_CTRLR0_SCPH_Pos \

    (8UL)


#define QSPI_CORE_CORE_CTRLR0_SCPH_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SCPH_Pos)


#define QSPI_CORE_CORE_CTRLR0_SCPH_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SCPH_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SCPH_MIDDLEBIT \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SCPH_STARTBIT \

    (0x1UL)


/* SCPOL @Bit 9 : Serial Clock Polarity. */


#define QSPI_CORE_CORE_CTRLR0_SCPOL_Pos \

    (9UL)


#define QSPI_CORE_CORE_CTRLR0_SCPOL_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SCPOL_Pos)


#define QSPI_CORE_CORE_CTRLR0_SCPOL_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SCPOL_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVEHIGH \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVELOW \

    (0x1UL)


/* TMOD @Bits 10..11 : Transfer Mode. */


#define QSPI_CORE_CORE_CTRLR0_TMOD_Pos \

    (10UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_Msk \

    (0x3UL << QSPI_CORE_CORE_CTRLR0_TMOD_Pos)


#define QSPI_CORE_CORE_CTRLR0_TMOD_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_Max \

    (0x3UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_TXANDRX \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_TXONLY \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_RXONLY \

    (0x2UL)


#define QSPI_CORE_CORE_CTRLR0_TMOD_EEPROMREAD \

    (0x3UL)


/* SLVOE @Bit 12 : Target Output Enable. */


#define QSPI_CORE_CORE_CTRLR0_SLVOE_Pos \

    (12UL)


#define QSPI_CORE_CORE_CTRLR0_SLVOE_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SLVOE_Pos)


#define QSPI_CORE_CORE_CTRLR0_SLVOE_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SLVOE_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SLVOE_ENABLED \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SLVOE_DISABLED \

    (0x1UL)


/* SRL @Bit 13 : Shift Register Loop. */


#define QSPI_CORE_CORE_CTRLR0_SRL_Pos \

    (13UL)


#define QSPI_CORE_CORE_CTRLR0_SRL_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SRL_Pos)


#define QSPI_CORE_CORE_CTRLR0_SRL_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SRL_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SRL_NORMALMODE \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SRL_TESTINGMODE \

    (0x1UL)


/* SSTE @Bit 14 : Target Select Toggle Enable. */


#define QSPI_CORE_CORE_CTRLR0_SSTE_Pos \

    (14UL)


#define QSPI_CORE_CORE_CTRLR0_SSTE_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SSTE_Pos)


#define QSPI_CORE_CORE_CTRLR0_SSTE_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SSTE_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SSTE_TOGGLEDISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SSTE_TOGGLEEN \

    (0x1UL)


/* RSVDCTRLR015 @Bit 15 : (unspecified) */


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Pos \

    (15UL)


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR015_Pos)


/* CFS @Bits 16..19 : Control Frame Size. */


#define QSPI_CORE_CORE_CTRLR0_CFS_Pos \

    (16UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_Msk \

    (0xFUL << QSPI_CORE_CORE_CTRLR0_CFS_Pos)


#define QSPI_CORE_CORE_CTRLR0_CFS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_Max \

    (0xFUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE01BIT \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE02BIT \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE03BIT \

    (0x2UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE04BIT \

    (0x3UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE05BIT \

    (0x4UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE06BIT \

    (0x5UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE07BIT \

    (0x6UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE08BIT \

    (0x7UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE09BIT \

    (0x8UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE10BIT \

    (0x9UL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE11BIT \

    (0xAUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE12BIT \

    (0xBUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE13BIT \

    (0xCUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE14BIT \

    (0xDUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE15BIT \

    (0xEUL)


#define QSPI_CORE_CORE_CTRLR0_CFS_SIZE16BIT \

    (0xFUL)


/* RSVDCTRLR02021 @Bits 20..21 : (unspecified) */


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Pos \

    (20UL)


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Msk \

    (0x3UL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02021_Pos)


/* SPIFRF @Bits 22..23 : SPI Frame Format */


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_Pos \

    (22UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_Msk \

    (0x3UL << QSPI_CORE_CORE_CTRLR0_SPIFRF_Pos)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_Max \

    (0x3UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_SPISTANDARD \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIDUAL \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIQUAD \

    (0x2UL)


#define QSPI_CORE_CORE_CTRLR0_SPIFRF_SPIOCTAL \

    (0x3UL)


/* SPIHYPERBUSEN @Bit 24 : SPI Hyperbus Frame format enable. */


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Pos \

    (24UL)


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Pos)


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIHYPERBUSEN_ENABLE \

    (0x1UL)


/* SPIDWSEN @Bit 25 : Enable Dynamic wait states in SPI mode of operation. This field is only applicable when CTRLR0.FRF is set

 *                    to 0 (Motorola SPI Frame Format). */


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Pos \

    (25UL)


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Pos)


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SPIDWSEN_ENABLE \

    (0x1UL)


/* CLKLOOPEN @Bit 26 : Clock loop back enable bit. Once this bit is set to 1, QSPI CORE will use looped back clock (mst_sclk_in)

 *                     to capture read data */


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Pos \

    (26UL)


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Pos)


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_CLKLOOPEN_ENABLE \

    (0x1UL)


/* RSVDCTRLR02730 @Bits 27..30 : (unspecified) */


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Pos \

    (27UL)


#define QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Msk \

    (0xFUL << QSPI_CORE_CORE_CTRLR0_RSVDCTRLR02730_Pos)


/* SQSPIISMST @Bit 31 : This field selects if QSPI CORE is working in Controller or Target mode */


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Pos \

    (31UL)


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Msk \

    (0x1UL << QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Pos)


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Min \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_Max \

    (0x1UL)


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_TARGET \

    (0x0UL)


#define QSPI_CORE_CORE_CTRLR0_SQSPIISMST_CONTROLLER \

    (0x1UL)


/* QSPI_CORE_CORE_CTRLR1: Control Register 1 */


#define QSPI_CORE_CORE_CTRLR1_ResetValue \

    (0x00000000UL)


/* NDF @Bits 0..15 : Number of Data Frames. */

#define QSPI_CORE_CORE_CTRLR1_NDF_Pos (0UL)


#define QSPI_CORE_CORE_CTRLR1_NDF_Msk \

    (0xFFFFUL << QSPI_CORE_CORE_CTRLR1_NDF_Pos)


/* RSVDCTRLR1 @Bits 16..31 : (unspecified) */


#define QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Pos \

    (16UL)


#define QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Msk \

    (0xFFFFUL << QSPI_CORE_CORE_CTRLR1_RSVDCTRLR1_Pos)


/* QSPI_CORE_CORE_SQSPIENR: SQSPI Enable Register */


#define QSPI_CORE_CORE_SQSPIENR_ResetValue \

    (0x00000000UL)


/* SQSPICEN @Bit 0 : SQSPI Enable. */


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Pos \

    (0UL)


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Pos)


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Min \

    (0x0UL)


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_Max \

    (0x1UL)


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_SQSPIENR_SQSPICEN_ENABLED \

    (0x1UL)


/* RSVDSQSPIENR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Pos \

    (1UL)


#define QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_SQSPIENR_RSVDSQSPIENR_Pos)


/* QSPI_CORE_CORE_MWCR: Microwire Control Register */


#define QSPI_CORE_CORE_MWCR_ResetValue \

    (0x00000000UL)


/* MWMOD @Bit 0 : Microwire Transfer Mode. */

#define QSPI_CORE_CORE_MWCR_MWMOD_Pos (0UL)


#define QSPI_CORE_CORE_MWCR_MWMOD_Msk \

    (0x1UL << QSPI_CORE_CORE_MWCR_MWMOD_Pos)


#define QSPI_CORE_CORE_MWCR_MWMOD_Min \

    (0x0UL)


#define QSPI_CORE_CORE_MWCR_MWMOD_Max \

    (0x1UL)


#define QSPI_CORE_CORE_MWCR_MWMOD_NONSEQUENTIAL \

    (0x0UL)


#define QSPI_CORE_CORE_MWCR_MWMOD_SEQUENTIAL \

    (0x1UL)


/* MDD @Bit 1 : Microwire Control. */

#define QSPI_CORE_CORE_MWCR_MDD_Pos (1UL)


#define QSPI_CORE_CORE_MWCR_MDD_Msk \

    (0x1UL << QSPI_CORE_CORE_MWCR_MDD_Pos)


#define QSPI_CORE_CORE_MWCR_MDD_Min (0x0UL)

#define QSPI_CORE_CORE_MWCR_MDD_Max (0x1UL)


#define QSPI_CORE_CORE_MWCR_MDD_RECEIVE \

    (0x0UL)


#define QSPI_CORE_CORE_MWCR_MDD_TRANSMIT \

    (0x1UL)


/* MHS @Bit 2 : Microwire Handshaking. */

#define QSPI_CORE_CORE_MWCR_MHS_Pos (2UL)


#define QSPI_CORE_CORE_MWCR_MHS_Msk \

    (0x1UL << QSPI_CORE_CORE_MWCR_MHS_Pos)


#define QSPI_CORE_CORE_MWCR_MHS_Min (0x0UL)

#define QSPI_CORE_CORE_MWCR_MHS_Max (0x1UL)


#define QSPI_CORE_CORE_MWCR_MHS_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_MWCR_MHS_ENABLED \

    (0x1UL)


/* RSVDMWCR @Bits 3..31 : (unspecified) */


#define QSPI_CORE_CORE_MWCR_RSVDMWCR_Pos \

    (3UL)


#define QSPI_CORE_CORE_MWCR_RSVDMWCR_Msk \

    (0x1FFFFFFFUL << QSPI_CORE_CORE_MWCR_RSVDMWCR_Pos)


/* QSPI_CORE_CORE_SER: Target Enable Register */


#define QSPI_CORE_CORE_SER_ResetValue \

    (0x00000000UL)


/* SER @Bits 0..3 : Chip Select Enable Flag. */

#define QSPI_CORE_CORE_SER_SER_Pos (0UL)


#define QSPI_CORE_CORE_SER_SER_Msk \

    (0xFUL << QSPI_CORE_CORE_SER_SER_Pos)


/* RSVDSER @Bits 4..31 : (unspecified) */


#define QSPI_CORE_CORE_SER_RSVDSER_Pos \

    (4UL)


#define QSPI_CORE_CORE_SER_RSVDSER_Msk \

    (0xFFFFFFFUL << QSPI_CORE_CORE_SER_RSVDSER_Pos)


/* QSPI_CORE_CORE_BAUDR: Baud Rate Select */


#define QSPI_CORE_CORE_BAUDR_ResetValue \

    (0x00000002UL)


/* RSVDBAUDR0 @Bit 0 : (unspecified) */


#define QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Pos \

    (0UL)


#define QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Msk \

    (0x1UL << QSPI_CORE_CORE_BAUDR_RSVDBAUDR0_Pos)


/* SCKDV @Bits 1..15 : SQSPI Clock Divider. */


#define QSPI_CORE_CORE_BAUDR_SCKDV_Pos \

    (1UL)


#define QSPI_CORE_CORE_BAUDR_SCKDV_Msk \

    (0x7FFFUL << QSPI_CORE_CORE_BAUDR_SCKDV_Pos)


/* RSVDBAUDR1631 @Bits 16..31 : (unspecified) */


#define QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Pos \

    (16UL)


#define QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Msk \

    (0xFFFFUL << QSPI_CORE_CORE_BAUDR_RSVDBAUDR1631_Pos)


/* QSPI_CORE_CORE_TXFTLR: Transmit FIFO Threshold Level */


#define QSPI_CORE_CORE_TXFTLR_ResetValue \

    (0x00080000UL)


/* TFT @Bits 0..3 : Transmit FIFO Threshold. */

#define QSPI_CORE_CORE_TXFTLR_TFT_Pos (0UL)


#define QSPI_CORE_CORE_TXFTLR_TFT_Msk \

    (0xFUL << QSPI_CORE_CORE_TXFTLR_TFT_Pos)


/* RSVDTXFTLR @Bits 4..15 : (unspecified) */


#define QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Pos \

    (4UL)


#define QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Msk \

    (0xFFFUL << QSPI_CORE_CORE_TXFTLR_RSVDTXFTLR_Pos)


/* TXFTHR @Bits 16..19 : Transfer start FIFO level. */


#define QSPI_CORE_CORE_TXFTLR_TXFTHR_Pos \

    (16UL)


#define QSPI_CORE_CORE_TXFTLR_TXFTHR_Msk \

    (0xFUL << QSPI_CORE_CORE_TXFTLR_TXFTHR_Pos)


/* RSVDTXFTHR @Bits 20..31 : (unspecified) */


#define QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Pos \

    (20UL)


#define QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Msk \

    (0xFFFUL << QSPI_CORE_CORE_TXFTLR_RSVDTXFTHR_Pos)


/* QSPI_CORE_CORE_RXFTLR: Receive FIFO Threshold Level */


#define QSPI_CORE_CORE_RXFTLR_ResetValue \

    (0x00000000UL)


/* RFT @Bits 0..3 : Receive FIFO Threshold. */

#define QSPI_CORE_CORE_RXFTLR_RFT_Pos (0UL)


#define QSPI_CORE_CORE_RXFTLR_RFT_Msk \

    (0xFUL << QSPI_CORE_CORE_RXFTLR_RFT_Pos)


/* RSVDRXFTLR @Bits 4..31 : (unspecified) */


#define QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Pos \

    (4UL)


#define QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Msk \

    (0xFFFFFFFUL << QSPI_CORE_CORE_RXFTLR_RSVDRXFTLR_Pos)


/* QSPI_CORE_CORE_TXFLR: Transmit FIFO Level Register */


#define QSPI_CORE_CORE_TXFLR_ResetValue \

    (0x00000000UL)


/* TXTFL @Bits 0..4 : Transmit FIFO Level. */


#define QSPI_CORE_CORE_TXFLR_TXTFL_Pos \

    (0UL)


#define QSPI_CORE_CORE_TXFLR_TXTFL_Msk \

    (0x1FUL << QSPI_CORE_CORE_TXFLR_TXTFL_Pos)


/* RSVDTXFLR @Bits 5..31 : (unspecified) */


#define QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Pos \

    (5UL)


#define QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Msk \

    (0x7FFFFFFUL << QSPI_CORE_CORE_TXFLR_RSVDTXFLR_Pos)


/* QSPI_CORE_CORE_RXFLR: Receive FIFO Level Register */


#define QSPI_CORE_CORE_RXFLR_ResetValue \

    (0x00000000UL)


/* RXTFL @Bits 0..4 : Receive FIFO Level. */


#define QSPI_CORE_CORE_RXFLR_RXTFL_Pos \

    (0UL)


#define QSPI_CORE_CORE_RXFLR_RXTFL_Msk \

    (0x1FUL << QSPI_CORE_CORE_RXFLR_RXTFL_Pos)


/* RSVDRXFLR @Bits 5..31 : (unspecified) */


#define QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Pos \

    (5UL)


#define QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Msk \

    (0x7FFFFFFUL << QSPI_CORE_CORE_RXFLR_RSVDRXFLR_Pos)


/* QSPI_CORE_CORE_SR: Status Register */


#define QSPI_CORE_CORE_SR_ResetValue \

    (0x00000006UL)


/* BUSY @Bit 0 : SQSPI Busy Flag. */

#define QSPI_CORE_CORE_SR_BUSY_Pos (0UL)


#define QSPI_CORE_CORE_SR_BUSY_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_BUSY_Pos)


#define QSPI_CORE_CORE_SR_BUSY_Min (0x0UL)

#define QSPI_CORE_CORE_SR_BUSY_Max (0x1UL)


#define QSPI_CORE_CORE_SR_BUSY_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_SR_BUSY_ACTIVE \

    (0x1UL)


/* TFNF @Bit 1 : Transmit FIFO Not Full. */

#define QSPI_CORE_CORE_SR_TFNF_Pos  (1UL)


#define QSPI_CORE_CORE_SR_TFNF_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_TFNF_Pos)


#define QSPI_CORE_CORE_SR_TFNF_Min  (0x0UL)

#define QSPI_CORE_CORE_SR_TFNF_Max  (0x1UL)

#define QSPI_CORE_CORE_SR_TFNF_FULL (0x0UL)


#define QSPI_CORE_CORE_SR_TFNF_NOTFULL \

    (0x1UL)


/* TFE @Bit 2 : Transmit FIFO Empty. */

#define QSPI_CORE_CORE_SR_TFE_Pos   (2UL)


#define QSPI_CORE_CORE_SR_TFE_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_TFE_Pos)


#define QSPI_CORE_CORE_SR_TFE_Min   (0x0UL)

#define QSPI_CORE_CORE_SR_TFE_Max   (0x1UL)


#define QSPI_CORE_CORE_SR_TFE_NOTEMPTY \

    (0x0UL)


#define QSPI_CORE_CORE_SR_TFE_EMPTY (0x1UL)


/* RFNE @Bit 3 : Receive FIFO Not Empty. */

#define QSPI_CORE_CORE_SR_RFNE_Pos (3UL)


#define QSPI_CORE_CORE_SR_RFNE_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_RFNE_Pos)


#define QSPI_CORE_CORE_SR_RFNE_Min (0x0UL)

#define QSPI_CORE_CORE_SR_RFNE_Max (0x1UL)


#define QSPI_CORE_CORE_SR_RFNE_EMPTY \

    (0x0UL)


#define QSPI_CORE_CORE_SR_RFNE_NOTEMPTY \

    (0x1UL)


/* RFF @Bit 4 : Receive FIFO Full. */

#define QSPI_CORE_CORE_SR_RFF_Pos  (4UL)


#define QSPI_CORE_CORE_SR_RFF_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_RFF_Pos)


#define QSPI_CORE_CORE_SR_RFF_Min  (0x0UL)

#define QSPI_CORE_CORE_SR_RFF_Max  (0x1UL)


#define QSPI_CORE_CORE_SR_RFF_NOTFULL \

    (0x0UL)


#define QSPI_CORE_CORE_SR_RFF_FULL (0x1UL)


/* TXE @Bit 5 : Transmission Error. */

#define QSPI_CORE_CORE_SR_TXE_Pos (5UL)


#define QSPI_CORE_CORE_SR_TXE_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_TXE_Pos)


#define QSPI_CORE_CORE_SR_TXE_Min (0x0UL)

#define QSPI_CORE_CORE_SR_TXE_Max (0x1UL)


#define QSPI_CORE_CORE_SR_TXE_NOERROR \

    (0x0UL)


#define QSPI_CORE_CORE_SR_TXE_TXERROR \

    (0x1UL)


/* DCOL @Bit 6 : Data Collision Error. */

#define QSPI_CORE_CORE_SR_DCOL_Pos (6UL)


#define QSPI_CORE_CORE_SR_DCOL_Msk \

    (0x1UL << QSPI_CORE_CORE_SR_DCOL_Pos)


#define QSPI_CORE_CORE_SR_DCOL_Min (0x0UL)

#define QSPI_CORE_CORE_SR_DCOL_Max (0x1UL)


#define QSPI_CORE_CORE_SR_DCOL_NOERRORCONDITION \

    (0x0UL)


#define QSPI_CORE_CORE_SR_DCOL_TXCOLLISIONERROR \

    (0x1UL)


/* RSVDSR @Bits 7..14 : (unspecified) */

#define QSPI_CORE_CORE_SR_RSVDSR_Pos (7UL)


#define QSPI_CORE_CORE_SR_RSVDSR_Msk \

    (0xFFUL << QSPI_CORE_CORE_SR_RSVDSR_Pos)


/* CMPLTDDF @Bits 15..31 : Completed Data frames */


#define QSPI_CORE_CORE_SR_CMPLTDDF_Pos \

    (15UL)


#define QSPI_CORE_CORE_SR_CMPLTDDF_Msk \

    (0x1FFFFUL << QSPI_CORE_CORE_SR_CMPLTDDF_Pos)


/* QSPI_CORE_CORE_IMR: Interrupt Mask Register */


#define QSPI_CORE_CORE_IMR_ResetValue \

    (0x0000043FUL)


/* TXEIM @Bit 0 : Transmit FIFO Empty Interrupt Mask */

#define QSPI_CORE_CORE_IMR_TXEIM_Pos (0UL)


#define QSPI_CORE_CORE_IMR_TXEIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_TXEIM_Pos)


#define QSPI_CORE_CORE_IMR_TXEIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXEIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_TXEIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXEIM_UNMASKED \

    (0x1UL)


/* TXOIM @Bit 1 : Transmit FIFO Overflow Interrupt Mask */

#define QSPI_CORE_CORE_IMR_TXOIM_Pos (1UL)


#define QSPI_CORE_CORE_IMR_TXOIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_TXOIM_Pos)


#define QSPI_CORE_CORE_IMR_TXOIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXOIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_TXOIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXOIM_UNMASKED \

    (0x1UL)


/* RXUIM @Bit 2 : Receive FIFO Underflow Interrupt Mask */

#define QSPI_CORE_CORE_IMR_RXUIM_Pos (2UL)


#define QSPI_CORE_CORE_IMR_RXUIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_RXUIM_Pos)


#define QSPI_CORE_CORE_IMR_RXUIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXUIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_RXUIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXUIM_UNMASKED \

    (0x1UL)


/* RXOIM @Bit 3 : Receive FIFO Overflow Interrupt Mask */

#define QSPI_CORE_CORE_IMR_RXOIM_Pos (3UL)


#define QSPI_CORE_CORE_IMR_RXOIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_RXOIM_Pos)


#define QSPI_CORE_CORE_IMR_RXOIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXOIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_RXOIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXOIM_UNMASKED \

    (0x1UL)


/* RXFIM @Bit 4 : Receive FIFO Full Interrupt Mask */

#define QSPI_CORE_CORE_IMR_RXFIM_Pos (4UL)


#define QSPI_CORE_CORE_IMR_RXFIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_RXFIM_Pos)


#define QSPI_CORE_CORE_IMR_RXFIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXFIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_RXFIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_RXFIM_UNMASKED \

    (0x1UL)


/* MSTIM @Bit 5 : Multi-Controller Contention Interrupt Mask. This bit field is not present if the QSPI CORE is configured as a

 *                serial-controller device. */


#define QSPI_CORE_CORE_IMR_MSTIM_Pos (5UL)


#define QSPI_CORE_CORE_IMR_MSTIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_MSTIM_Pos)


#define QSPI_CORE_CORE_IMR_MSTIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_MSTIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_MSTIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_MSTIM_UNMASKED \

    (0x1UL)


/* XRXOIM @Bit 6 : XIP Receive FIFO Overflow Interrupt Mask */

#define QSPI_CORE_CORE_IMR_XRXOIM_Pos (6UL)


#define QSPI_CORE_CORE_IMR_XRXOIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_XRXOIM_Pos)


#define QSPI_CORE_CORE_IMR_XRXOIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_XRXOIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_XRXOIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_XRXOIM_UNMASKED \

    (0x1UL)


/* TXUIM @Bit 7 : Transmit FIFO Underflow Interrupt Mask */

#define QSPI_CORE_CORE_IMR_TXUIM_Pos (7UL)


#define QSPI_CORE_CORE_IMR_TXUIM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_TXUIM_Pos)


#define QSPI_CORE_CORE_IMR_TXUIM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXUIM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_TXUIM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_TXUIM_UNMASKED \

    (0x1UL)


/* AXIEM @Bit 8 : AXI Error Interrupt Mask */

#define QSPI_CORE_CORE_IMR_AXIEM_Pos (8UL)


#define QSPI_CORE_CORE_IMR_AXIEM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_AXIEM_Pos)


#define QSPI_CORE_CORE_IMR_AXIEM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_AXIEM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_AXIEM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_AXIEM_UNMASKED \

    (0x1UL)


/* RSVD9IMR @Bit 9 : (unspecified) */


#define QSPI_CORE_CORE_IMR_RSVD9IMR_Pos \

    (9UL)


#define QSPI_CORE_CORE_IMR_RSVD9IMR_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_RSVD9IMR_Pos)


/* SPITEM @Bit 10 : SPI Transmit Error Interrupt Mask */


#define QSPI_CORE_CORE_IMR_SPITEM_Pos \

    (10UL)


#define QSPI_CORE_CORE_IMR_SPITEM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_SPITEM_Pos)


#define QSPI_CORE_CORE_IMR_SPITEM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_SPITEM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_SPITEM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_SPITEM_UNMASKED \

    (0x1UL)


/* DONEM @Bit 11 : SQSPI Done Interrupt Mask */

#define QSPI_CORE_CORE_IMR_DONEM_Pos (11UL)


#define QSPI_CORE_CORE_IMR_DONEM_Msk \

    (0x1UL << QSPI_CORE_CORE_IMR_DONEM_Pos)


#define QSPI_CORE_CORE_IMR_DONEM_Min \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_DONEM_Max \

    (0x1UL)


#define QSPI_CORE_CORE_IMR_DONEM_MASKED \

    (0x0UL)


#define QSPI_CORE_CORE_IMR_DONEM_UNMASKED \

    (0x1UL)


/* RSVD1231IMR @Bits 12..31 : (unspecified) */


#define QSPI_CORE_CORE_IMR_RSVD1231IMR_Pos \

    (12UL)


#define QSPI_CORE_CORE_IMR_RSVD1231IMR_Msk \

    (0xFFFFFUL << QSPI_CORE_CORE_IMR_RSVD1231IMR_Pos)


/* QSPI_CORE_CORE_ISR: Interrupt Status Register */


#define QSPI_CORE_CORE_ISR_ResetValue \

    (0x00000000UL)


/* TXEIS @Bit 0 : Transmit FIFO Empty Interrupt Status */

#define QSPI_CORE_CORE_ISR_TXEIS_Pos (0UL)


#define QSPI_CORE_CORE_ISR_TXEIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_TXEIS_Pos)


#define QSPI_CORE_CORE_ISR_TXEIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXEIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_TXEIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXEIS_ACTIVE \

    (0x1UL)


/* TXOIS @Bit 1 : Transmit FIFO Overflow Interrupt Status */

#define QSPI_CORE_CORE_ISR_TXOIS_Pos (1UL)


#define QSPI_CORE_CORE_ISR_TXOIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_TXOIS_Pos)


#define QSPI_CORE_CORE_ISR_TXOIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXOIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_TXOIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXOIS_ACTIVE \

    (0x1UL)


/* RXUIS @Bit 2 : Receive FIFO Underflow Interrupt Status */

#define QSPI_CORE_CORE_ISR_RXUIS_Pos (2UL)


#define QSPI_CORE_CORE_ISR_RXUIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_RXUIS_Pos)


#define QSPI_CORE_CORE_ISR_RXUIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXUIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_RXUIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXUIS_ACTIVE \

    (0x1UL)


/* RXOIS @Bit 3 : Receive FIFO Overflow Interrupt Status */

#define QSPI_CORE_CORE_ISR_RXOIS_Pos (3UL)


#define QSPI_CORE_CORE_ISR_RXOIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_RXOIS_Pos)


#define QSPI_CORE_CORE_ISR_RXOIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXOIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_RXOIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXOIS_ACTIVE \

    (0x1UL)


/* RXFIS @Bit 4 : Receive FIFO Full Interrupt Status */

#define QSPI_CORE_CORE_ISR_RXFIS_Pos (4UL)


#define QSPI_CORE_CORE_ISR_RXFIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_RXFIS_Pos)


#define QSPI_CORE_CORE_ISR_RXFIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXFIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_RXFIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_RXFIS_ACTIVE \

    (0x1UL)


/* MSTIS @Bit 5 : Multi-Controller Contention Interrupt Status. This bit field is not present */

#define QSPI_CORE_CORE_ISR_MSTIS_Pos (5UL)


#define QSPI_CORE_CORE_ISR_MSTIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_MSTIS_Pos)


#define QSPI_CORE_CORE_ISR_MSTIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_MSTIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_MSTIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_MSTIS_ACTIVE \

    (0x1UL)


/* XRXOIS @Bit 6 : XIP Receive FIFO Overflow Interrupt Status */

#define QSPI_CORE_CORE_ISR_XRXOIS_Pos (6UL)


#define QSPI_CORE_CORE_ISR_XRXOIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_XRXOIS_Pos)


#define QSPI_CORE_CORE_ISR_XRXOIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_XRXOIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_XRXOIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_XRXOIS_ACTIVE \

    (0x1UL)


/* TXUIS @Bit 7 : Transmit FIFO Underflow Interrupt Status */

#define QSPI_CORE_CORE_ISR_TXUIS_Pos (7UL)


#define QSPI_CORE_CORE_ISR_TXUIS_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_TXUIS_Pos)


#define QSPI_CORE_CORE_ISR_TXUIS_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXUIS_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_TXUIS_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_TXUIS_ACTIVE \

    (0x1UL)


/* AXIES @Bit 8 : AXI Error Interrupt Status */

#define QSPI_CORE_CORE_ISR_AXIES_Pos (8UL)


#define QSPI_CORE_CORE_ISR_AXIES_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_AXIES_Pos)


#define QSPI_CORE_CORE_ISR_AXIES_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_AXIES_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_AXIES_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_AXIES_ACTIVE \

    (0x1UL)


/* RSVD9RISR @Bit 9 : (unspecified) */


#define QSPI_CORE_CORE_ISR_RSVD9RISR_Pos \

    (9UL)


#define QSPI_CORE_CORE_ISR_RSVD9RISR_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_RSVD9RISR_Pos)


/* SPITES @Bit 10 : SPI Transmit Error Interrupt */


#define QSPI_CORE_CORE_ISR_SPITES_Pos \

    (10UL)


#define QSPI_CORE_CORE_ISR_SPITES_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_SPITES_Pos)


#define QSPI_CORE_CORE_ISR_SPITES_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_SPITES_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_SPITES_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_SPITES_ACTIVE \

    (0x1UL)


/* DONES @Bit 11 : SQSPI Done Interrupt Status */

#define QSPI_CORE_CORE_ISR_DONES_Pos (11UL)


#define QSPI_CORE_CORE_ISR_DONES_Msk \

    (0x1UL << QSPI_CORE_CORE_ISR_DONES_Pos)


#define QSPI_CORE_CORE_ISR_DONES_Min \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_DONES_Max \

    (0x1UL)


#define QSPI_CORE_CORE_ISR_DONES_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_ISR_DONES_ACTIVE \

    (0x1UL)


/* RSVD1231RISR @Bits 12..31 : (unspecified) */


#define QSPI_CORE_CORE_ISR_RSVD1231RISR_Pos \

    (12UL)


#define QSPI_CORE_CORE_ISR_RSVD1231RISR_Msk \

    (0xFFFFFUL << QSPI_CORE_CORE_ISR_RSVD1231RISR_Pos)


/* QSPI_CORE_CORE_RISR: Raw Interrupt Status Register */


#define QSPI_CORE_CORE_RISR_ResetValue \

    (0x00000000UL)


/* TXEIR @Bit 0 : Transmit FIFO Empty Raw Interrupt Status */

#define QSPI_CORE_CORE_RISR_TXEIR_Pos (0UL)


#define QSPI_CORE_CORE_RISR_TXEIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_TXEIR_Pos)


#define QSPI_CORE_CORE_RISR_TXEIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXEIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_TXEIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXEIR_ACTIVE \

    (0x1UL)


/* TXOIR @Bit 1 : Transmit FIFO Overflow Raw Interrupt Status */

#define QSPI_CORE_CORE_RISR_TXOIR_Pos (1UL)


#define QSPI_CORE_CORE_RISR_TXOIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_TXOIR_Pos)


#define QSPI_CORE_CORE_RISR_TXOIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXOIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_TXOIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXOIR_ACTIVE \

    (0x1UL)


/* RXUIR @Bit 2 : Receive FIFO Underflow Raw Interrupt Status */

#define QSPI_CORE_CORE_RISR_RXUIR_Pos (2UL)


#define QSPI_CORE_CORE_RISR_RXUIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_RXUIR_Pos)


#define QSPI_CORE_CORE_RISR_RXUIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXUIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_RXUIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXUIR_ACTIVE \

    (0x1UL)


/* RXOIR @Bit 3 : Receive FIFO Overflow Raw Interrupt Status */

#define QSPI_CORE_CORE_RISR_RXOIR_Pos (3UL)


#define QSPI_CORE_CORE_RISR_RXOIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_RXOIR_Pos)


#define QSPI_CORE_CORE_RISR_RXOIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXOIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_RXOIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXOIR_ACTIVE \

    (0x1UL)


/* RXFIR @Bit 4 : Receive FIFO Full Raw Interrupt Status */

#define QSPI_CORE_CORE_RISR_RXFIR_Pos (4UL)


#define QSPI_CORE_CORE_RISR_RXFIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_RXFIR_Pos)


#define QSPI_CORE_CORE_RISR_RXFIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXFIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_RXFIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_RXFIR_ACTIVE \

    (0x1UL)


/* MSTIR @Bit 5 : Multi-Controller Contention Raw Interrupt Status. This bit field is not present if the QSPI CORE is configured

 *                as a serial-target device. */


#define QSPI_CORE_CORE_RISR_MSTIR_Pos (5UL)


#define QSPI_CORE_CORE_RISR_MSTIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_MSTIR_Pos)


#define QSPI_CORE_CORE_RISR_MSTIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_MSTIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_MSTIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_MSTIR_ACTIVE \

    (0x1UL)


/* XRXOIR @Bit 6 : XIP Receive FIFO Overflow Raw Interrupt Status */


#define QSPI_CORE_CORE_RISR_XRXOIR_Pos \

    (6UL)


#define QSPI_CORE_CORE_RISR_XRXOIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_XRXOIR_Pos)


#define QSPI_CORE_CORE_RISR_XRXOIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_XRXOIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_XRXOIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_XRXOIR_ACTIVE \

    (0x1UL)


/* TXUIR @Bit 7 : Transmit FIFO Underflow Interrupt Raw Status */

#define QSPI_CORE_CORE_RISR_TXUIR_Pos (7UL)


#define QSPI_CORE_CORE_RISR_TXUIR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_TXUIR_Pos)


#define QSPI_CORE_CORE_RISR_TXUIR_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXUIR_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_TXUIR_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_TXUIR_ACTIVE \

    (0x1UL)


/* AXIER @Bit 8 : AXI Error Interrupt Raw Status */

#define QSPI_CORE_CORE_RISR_AXIER_Pos (8UL)


#define QSPI_CORE_CORE_RISR_AXIER_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_AXIER_Pos)


#define QSPI_CORE_CORE_RISR_AXIER_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_AXIER_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_AXIER_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_AXIER_ACTIVE \

    (0x1UL)


/* RSVD9RISR @Bit 9 : (unspecified) */


#define QSPI_CORE_CORE_RISR_RSVD9RISR_Pos \

    (9UL)


#define QSPI_CORE_CORE_RISR_RSVD9RISR_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_RSVD9RISR_Pos)


/* SPITER @Bit 10 : SPI Transmit Error Interrupt status. */


#define QSPI_CORE_CORE_RISR_SPITER_Pos \

    (10UL)


#define QSPI_CORE_CORE_RISR_SPITER_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_SPITER_Pos)


#define QSPI_CORE_CORE_RISR_SPITER_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_SPITER_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_SPITER_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_SPITER_ACTIVE \

    (0x1UL)


/* DONER @Bit 11 : SQSPI Done Interrupt Raw Status */


#define QSPI_CORE_CORE_RISR_DONER_Pos \

    (11UL)


#define QSPI_CORE_CORE_RISR_DONER_Msk \

    (0x1UL << QSPI_CORE_CORE_RISR_DONER_Pos)


#define QSPI_CORE_CORE_RISR_DONER_Min \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_DONER_Max \

    (0x1UL)


#define QSPI_CORE_CORE_RISR_DONER_INACTIVE \

    (0x0UL)


#define QSPI_CORE_CORE_RISR_DONER_ACTIVE \

    (0x1UL)


/* RSVD1231RISR @Bits 12..31 : (unspecified) */


#define QSPI_CORE_CORE_RISR_RSVD1231RISR_Pos \

    (12UL)


#define QSPI_CORE_CORE_RISR_RSVD1231RISR_Msk \

    (0xFFFFFUL << QSPI_CORE_CORE_RISR_RSVD1231RISR_Pos)


/* QSPI_CORE_CORE_TXEICR: Transmit FIFO Error Interrupt Clear Register Register */


#define QSPI_CORE_CORE_TXEICR_ResetValue \

    (0x00000000UL)


/* TXEICR @Bit 0 : Clear Transmit FIFO Overflow/Underflow Interrupt. */


#define QSPI_CORE_CORE_TXEICR_TXEICR_Pos \

    (0UL)


#define QSPI_CORE_CORE_TXEICR_TXEICR_Msk \

    (0x1UL << QSPI_CORE_CORE_TXEICR_TXEICR_Pos)


/* RSVDTXEICR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Pos \

    (1UL)


#define QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_TXEICR_RSVDTXEICR_Pos)


/* QSPI_CORE_CORE_RXOICR: Receive FIFO Overflow Interrupt Clear Register */


#define QSPI_CORE_CORE_RXOICR_ResetValue \

    (0x00000000UL)


/* RXOICR @Bit 0 : Clear Receive FIFO Overflow Interrupt. */


#define QSPI_CORE_CORE_RXOICR_RXOICR_Pos \

    (0UL)


#define QSPI_CORE_CORE_RXOICR_RXOICR_Msk \

    (0x1UL << QSPI_CORE_CORE_RXOICR_RXOICR_Pos)


/* RSVDRXOICR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Pos \

    (1UL)


#define QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_RXOICR_RSVDRXOICR_Pos)


/* QSPI_CORE_CORE_RXUICR: Receive FIFO Underflow Interrupt Clear Register */


#define QSPI_CORE_CORE_RXUICR_ResetValue \

    (0x00000000UL)


/* RXUICR @Bit 0 : Clear Receive FIFO Underflow Interrupt. */


#define QSPI_CORE_CORE_RXUICR_RXUICR_Pos \

    (0UL)


#define QSPI_CORE_CORE_RXUICR_RXUICR_Msk \

    (0x1UL << QSPI_CORE_CORE_RXUICR_RXUICR_Pos)


/* RSVDRXUICR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Pos \

    (1UL)


#define QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_RXUICR_RSVDRXUICR_Pos)


/* QSPI_CORE_CORE_MSTICR: Multi-Controller Interrupt Clear Register */


#define QSPI_CORE_CORE_MSTICR_ResetValue \

    (0x00000000UL)


/* MSTICR @Bit 0 : Clear Multi-Controller Contention Interrupt. */


#define QSPI_CORE_CORE_MSTICR_MSTICR_Pos \

    (0UL)


#define QSPI_CORE_CORE_MSTICR_MSTICR_Msk \

    (0x1UL << QSPI_CORE_CORE_MSTICR_MSTICR_Pos)


/* RSVDMSTICR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Pos \

    (1UL)


#define QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_MSTICR_RSVDMSTICR_Pos)


/* QSPI_CORE_CORE_ICR: Interrupt Clear Register */


#define QSPI_CORE_CORE_ICR_ResetValue \

    (0x00000000UL)


/* ICR @Bit 0 : Clear Interrupts. */

#define QSPI_CORE_CORE_ICR_ICR_Pos (0UL)


#define QSPI_CORE_CORE_ICR_ICR_Msk \

    (0x1UL << QSPI_CORE_CORE_ICR_ICR_Pos)


/* RSVDICR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_ICR_RSVDICR_Pos \

    (1UL)


#define QSPI_CORE_CORE_ICR_RSVDICR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_ICR_RSVDICR_Pos)


/* QSPI_CORE_CORE_DMACR: DMA Control Register */


#define QSPI_CORE_CORE_DMACR_ResetValue \

    (0x00000000UL)


/* RDMAE @Bit 0 : Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. */


#define QSPI_CORE_CORE_DMACR_RDMAE_Pos \

    (0UL)


#define QSPI_CORE_CORE_DMACR_RDMAE_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_RDMAE_Pos)


#define QSPI_CORE_CORE_DMACR_RDMAE_Min \

    (0x0UL)


#define QSPI_CORE_CORE_DMACR_RDMAE_Max \

    (0x1UL)


#define QSPI_CORE_CORE_DMACR_RDMAE_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_DMACR_RDMAE_ENABLED \

    (0x1UL)


/* TDMAE @Bit 1 : Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. */


#define QSPI_CORE_CORE_DMACR_TDMAE_Pos \

    (1UL)


#define QSPI_CORE_CORE_DMACR_TDMAE_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_TDMAE_Pos)


#define QSPI_CORE_CORE_DMACR_TDMAE_Min \

    (0x0UL)


#define QSPI_CORE_CORE_DMACR_TDMAE_Max \

    (0x1UL)


#define QSPI_CORE_CORE_DMACR_TDMAE_DISABLE \

    (0x0UL)


#define QSPI_CORE_CORE_DMACR_TDMAE_ENABLED \

    (0x1UL)


/* IDMAE @Bit 2 : Internal DMA Enable. This bit should be enabled only when CTRLR0.FRF = 0 (Motorola SPI) and CTRLR0.SPI_FRF >

 *                0. */


#define QSPI_CORE_CORE_DMACR_IDMAE_Pos \

    (2UL)


#define QSPI_CORE_CORE_DMACR_IDMAE_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_IDMAE_Pos)


/* ATW @Bits 3..4 : AXI transfer width for DMA transfers mapped to arsize/awsize. This value must be less than or equal to

 *                  SQSPIC_AXI_DW. Values: */


#define QSPI_CORE_CORE_DMACR_ATW_Pos (3UL)


#define QSPI_CORE_CORE_DMACR_ATW_Msk \

    (0x3UL << QSPI_CORE_CORE_DMACR_ATW_Pos)


/* RSVDDMACR5 @Bit 5 : (unspecified) */


#define QSPI_CORE_CORE_DMACR_RSVDDMACR5_Pos \

    (5UL)


#define QSPI_CORE_CORE_DMACR_RSVDDMACR5_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_RSVDDMACR5_Pos)


/* AINC @Bit 6 : Address Increment. Indicates whether to increment the AXI address on every transfer. */

#define QSPI_CORE_CORE_DMACR_AINC_Pos (6UL)


#define QSPI_CORE_CORE_DMACR_AINC_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_AINC_Pos)


/* RSVDDMACR7 @Bit 7 : (unspecified) */


#define QSPI_CORE_CORE_DMACR_RSVDDMACR7_Pos \

    (7UL)


#define QSPI_CORE_CORE_DMACR_RSVDDMACR7_Msk \

    (0x1UL << QSPI_CORE_CORE_DMACR_RSVDDMACR7_Pos)


/* ACACHE @Bits 8..11 : AXI arcache/awcache signal value. */


#define QSPI_CORE_CORE_DMACR_ACACHE_Pos \

    (8UL)


#define QSPI_CORE_CORE_DMACR_ACACHE_Msk \

    (0xFUL << QSPI_CORE_CORE_DMACR_ACACHE_Pos)


/* APROT @Bits 12..14 : AXI arprot/awprot signal value. */


#define QSPI_CORE_CORE_DMACR_APROT_Pos \

    (12UL)


#define QSPI_CORE_CORE_DMACR_APROT_Msk \

    (0x7UL << QSPI_CORE_CORE_DMACR_APROT_Pos)


/* AID @Bits 15..20 : AXI awid/arid signal value. */

#define QSPI_CORE_CORE_DMACR_AID_Pos (15UL)


#define QSPI_CORE_CORE_DMACR_AID_Msk \

    (0x3FUL << QSPI_CORE_CORE_DMACR_AID_Pos)


/* RSVDDMACR @Bits 21..31 : (unspecified) */


#define QSPI_CORE_CORE_DMACR_RSVDDMACR_Pos \

    (21UL)


#define QSPI_CORE_CORE_DMACR_RSVDDMACR_Msk \

    (0x7FFUL << QSPI_CORE_CORE_DMACR_RSVDDMACR_Pos)


/* QSPI_CORE_CORE_DMATDLR: DMA Transmit Data Level */


#define QSPI_CORE_CORE_DMATDLR_ResetValue \

    (0x00000000UL)


/* DMATDL @Bits 0..3 : Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit

 *                     logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of

 *                     valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. */


#define QSPI_CORE_CORE_DMATDLR_DMATDL_Pos \

    (0UL)


#define QSPI_CORE_CORE_DMATDLR_DMATDL_Msk \

    (0xFUL << QSPI_CORE_CORE_DMATDLR_DMATDL_Pos)


/* RSVDDMATDLR @Bits 4..31 : (unspecified) */


#define QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Pos \

    (4UL)


#define QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Msk \

    (0xFFFFFFFUL << QSPI_CORE_CORE_DMATDLR_RSVDDMATDLR_Pos)


/* QSPI_CORE_CORE_DMARDLR: DMA Receive Data Level */


#define QSPI_CORE_CORE_DMARDLR_ResetValue \

    (0x00000000UL)


/* DMARDL @Bits 0..3 : Receive Data Level. This bit field controls the level at which a DMA request is made by the receive

 *                     logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data

 *                     entries in the receive FIFO is equal to or above this field value + 1, and RDMAE=1. */


#define QSPI_CORE_CORE_DMARDLR_DMARDL_Pos \

    (0UL)


#define QSPI_CORE_CORE_DMARDLR_DMARDL_Msk \

    (0xFUL << QSPI_CORE_CORE_DMARDLR_DMARDL_Pos)


/* RSVDDMARDLR @Bits 4..31 : (unspecified) */


#define QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Pos \

    (4UL)


#define QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Msk \

    (0xFFFFFFFUL << QSPI_CORE_CORE_DMARDLR_RSVDDMARDLR_Pos)


/* QSPI_CORE_CORE_IDR: Identification Register */


#define QSPI_CORE_CORE_IDR_ResetValue \

    (0x51535049UL)


/* IDCODE @Bits 0..31 : Identification code. The register contains the identification code of the peripheral, which is written

 *                      into the register at configuration time using CoreConsultant. */


#define QSPI_CORE_CORE_IDR_IDCODE_Pos (0UL)


#define QSPI_CORE_CORE_IDR_IDCODE_Msk \

    (0xFFFFFFFFUL << QSPI_CORE_CORE_IDR_IDCODE_Pos)


/* QSPI_CORE_CORE_SQSPICVERSIONID: QSPI CORE component version */


#define QSPI_CORE_CORE_SQSPICVERSIONID_ResetValue \

    (0x00000000UL)


/* SQSPICCOMPVERSION @Bits 0..31 : Contains the hex representation of the sQSPI version. */


#define QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Pos \

    (0UL)


#define QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Msk \

    (0xFFFFFFFFUL << QSPI_CORE_CORE_SQSPICVERSIONID_SQSPICCOMPVERSION_Pos)


/* QSPI_CORE_CORE_DR: QSPI CORE Data Register */

#define QSPI_CORE_CORE_DR_MaxCount (36UL)

#define QSPI_CORE_CORE_DR_MaxIndex (35UL)

#define QSPI_CORE_CORE_DR_MinIndex (0UL)


#define QSPI_CORE_CORE_DR_ResetValue \

    (0x00000000UL)


/* DR @Bits 0..31 : Data Register. When writing to this register, you must right-justify the data. Read data are automatically

 *                  right-justified. */


#define QSPI_CORE_CORE_DR_DR_Pos (0UL)


#define QSPI_CORE_CORE_DR_DR_Msk \

    (0xFFFFFFFFUL << QSPI_CORE_CORE_DR_DR_Pos)


/* QSPI_CORE_CORE_RXSAMPLEDELAY: RX Sample Delay Register */


#define QSPI_CORE_CORE_RXSAMPLEDELAY_ResetValue \

    (0x00000000UL)


/* RSD @Bits 0..7 : Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input port. Each value

 */


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Pos \

    (0UL)


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Msk \

    (0xFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSD_Pos)


/* RSVD0RXSAMPLEDELAY @Bits 8..15 : (unspecified) */


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Pos \

    (8UL)


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Msk \

    (0xFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD0RXSAMPLEDELAY_Pos)


/* SE @Bit 16 : Receive Data (rxd) Sampling Edge. This register is used to decide the sampling edge for RXD signal with sqspiclk.

 *              Then this bit is set to 1 then negative edge of sqspiclk will be used to sample the incoming data, otherwise

 *              positive edge will be used for sampling. */


#define QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Pos \

    (16UL)


#define QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Msk \

    (0x1UL << QSPI_CORE_CORE_RXSAMPLEDELAY_SE_Pos)


/* RSVD1RXSAMPLEDELAY @Bits 17..31 : (unspecified) */


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Pos \

    (17UL)


#define QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Msk \

    (0x7FFFUL << QSPI_CORE_CORE_RXSAMPLEDELAY_RSVD1RXSAMPLEDELAY_Pos)


/* QSPI_CORE_CORE_SPICTRLR0: SPI_CTRLR0 - SPI Control Register */


#define QSPI_CORE_CORE_SPICTRLR0_ResetValue \

    (0x40000200UL)


/* TRANSTYPE @Bits 0..1 : Address and instruction transfer format. */


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Pos \

    (0UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Msk \

    (0x3UL << QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Pos)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Min \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_Max \

    (0x3UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT0 \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT1 \

    (0x1UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT2 \

    (0x2UL)


#define QSPI_CORE_CORE_SPICTRLR0_TRANSTYPE_TT3 \

    (0x3UL)


/* ADDRL @Bits 2..5 : This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the

 *                    FIFO the transfer can begin. */


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_Pos \

    (2UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_Msk \

    (0xFUL << QSPI_CORE_CORE_SPICTRLR0_ADDRL_Pos)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_Min \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_Max \

    (0xFUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL0 \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL4 \

    (0x1UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL8 \

    (0x2UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL12 \

    (0x3UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL16 \

    (0x4UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL20 \

    (0x5UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL24 \

    (0x6UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL28 \

    (0x7UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL32 \

    (0x8UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL36 \

    (0x9UL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL40 \

    (0xAUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL44 \

    (0xBUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL48 \

    (0xCUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL52 \

    (0xDUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL56 \

    (0xEUL)


#define QSPI_CORE_CORE_SPICTRLR0_ADDRL_ADDRL60 \

    (0xFUL)


/* RSVDSPICTRLR06 @Bit 6 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Pos \

    (6UL)


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR06_Pos)


/* XIPMDBITEN @Bit 7 : Mode bits enable in XIP mode. If this bit is set to 1, then in XIP mode of operation QSPI CORE will

 *                     insert mode bits after the address phase. These bits are set in register XIP_MODE_BITS register. */


#define QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Pos \

    (7UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPMDBITEN_Pos)


/* INSTL @Bits 8..9 : Enhanced SPI mode instruction length in bits. */


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_Pos \

    (8UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_Msk \

    (0x3UL << QSPI_CORE_CORE_SPICTRLR0_INSTL_Pos)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_Min \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_Max \

    (0x3UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL0 \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL4 \

    (0x1UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL8 \

    (0x2UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTL_INSTL16 \

    (0x3UL)


/* RSVDSPICTRLR010 @Bit 10 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Pos \

    (10UL)


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR010_Pos)


/* WAITCYCLES @Bits 11..15 : Wait cycles in Enhanced SPI mode between control frames transmit and data reception. Specified as

 *                           number of SPI clock cycles. */


#define QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Pos \

    (11UL)


#define QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Msk \

    (0x1FUL << QSPI_CORE_CORE_SPICTRLR0_WAITCYCLES_Pos)


/* SPIDDREN @Bit 16 : SPI DDR Enable bit. This will enable Dual-data rate transfers in Enhanced SPI frame formats of SPI. */


#define QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Pos \

    (16UL)


#define QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIDDREN_Pos)


/* INSTDDREN @Bit 17 : Instruction DDR Enable bit. This will enable Dual-data rate transfer for Instruction phase. */


#define QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Pos \

    (17UL)


#define QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_INSTDDREN_Pos)


/* SPIRXDSEN @Bit 18 : Read data strobe enable bit. Once this bit is set to 1 QSPI CORE will use Read data strobe (rxds) to

 *                     capture read data. */


#define QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Pos \

    (18UL)


#define QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIRXDSEN_Pos)


/* XIPDFSHC @Bit 19 : Fix DFS for XIP transfers. If this bit is set to 1 then data frame size for XIP transfers will be fixed to

 *                    the programmed value in CTRLR0.DFS. The number of data frames to fetch will be determined by HSIZE and

 *                    HBURST signals. If this bit is set to 0 then data frame size and number of data frames to fetch will be

 *                    determined by HSIZE and HBURST signals */


#define QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Pos \

    (19UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPDFSHC_Pos)


/* XIPINSTEN @Bit 20 : XIP instruction enable bit. If this bit is set to 1 then XIP transfers will also have instruction phase.

 *                     The instruction op-codes will be chosen from XIP_INCR_INST or XIP_WRAP_INST registers bases on AHB

 *                     transfer type. */


#define QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Pos \

    (20UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPINSTEN_Pos)


/* SQSPICXIPCONTXFEREN @Bit 21 : Enable continuous transfer in XIP mode. If this bit is set to 1 then continuous transfer mode in

 *                             XIP will be enabled, in this mode QSPI CORE will keep target selected until a non-XIP transfer is

 *                             detected on the AHB interface. */


#define QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Pos \

    (21UL)


#define QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SQSPICXIPCONTXFEREN_Pos)


/* RSVDSPICTRLR022 @Bit 22 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Pos \

    (22UL)


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR022_Pos)


/* RXDSVLEN @Bit 23 : RXDS variable latency enable bit. */


#define QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Pos \

    (23UL)


#define QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RXDSVLEN_Pos)


/* SPIDMEN @Bit 24 : SPI data mask enable bit. */


#define QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Pos \

    (24UL)


#define QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIDMEN_Pos)


/* SPIRXDSSIGEN @Bit 25 : Enable rxds signaling during address and command phase of Hyperbus transfer. */


#define QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Pos \

    (25UL)


#define QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_SPIRXDSSIGEN_Pos)


/* XIPMBL @Bits 26..27 : XIP Mode bits length. Sets the length of mode bits in XIP mode of operation. These bits are valid only

 *                       when SPI_CTRLR0.XIP_MD_BIT_EN is set to 1. */


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Pos \

    (26UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Msk \

    (0x3UL << QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Pos)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Min \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_Max \

    (0x3UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL2 \

    (0x0UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL4 \

    (0x1UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL8 \

    (0x2UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPMBL_MBL16 \

    (0x3UL)


/* RSVDSPICTRLR028 @Bit 28 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Pos \

    (28UL)


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR028_Pos)


/* XIPPREFETCHEN @Bit 29 : Enables XIP pre-fetch functionality in QSPI CORE. */


#define QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Pos \

    (29UL)


#define QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_XIPPREFETCHEN_Pos)


/* CLKSTRETCHEN @Bit 30 : Enables clock stretching capability in SPI transfers. */


#define QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Pos \

    (30UL)


#define QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_CLKSTRETCHEN_Pos)


/* RSVDSPICTRLR0 @Bit 31 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Pos \

    (31UL)


#define QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Msk \

    (0x1UL << QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Pos)


/* QSPI_CORE_CORE_SPICTRLR1: SPI Control 1 register */


#define QSPI_CORE_CORE_SPICTRLR1_ResetValue \

    (0x00000000UL)


/* DYNWS @Bits 0..2 : SPI Dynamic Wait states field. */


#define QSPI_CORE_CORE_SPICTRLR1_DYNWS_Pos \

    (0UL)


#define QSPI_CORE_CORE_SPICTRLR1_DYNWS_Msk \

    (0x7UL << QSPI_CORE_CORE_SPICTRLR1_DYNWS_Pos)


/* RSVDSPICTRLR137 @Bits 3..7 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Pos \

    (3UL)


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Msk \

    (0x1FUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR137_Pos)


/* MAXWS @Bits 8..11 : Maximum wait cycles allowed per transaction. */


#define QSPI_CORE_CORE_SPICTRLR1_MAXWS_Pos \

    (8UL)


#define QSPI_CORE_CORE_SPICTRLR1_MAXWS_Msk \

    (0xFUL << QSPI_CORE_CORE_SPICTRLR1_MAXWS_Pos)


/* RSVDSPICTRLR11215 @Bits 12..15 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Pos \

    (12UL)


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Msk \

    (0xFUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR11215_Pos)


/* CSMINHIGH @Bits 16..19 : Chip-Select Minimum HIGH period. */


#define QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Pos \

    (16UL)


#define QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Msk \

    (0xFUL << QSPI_CORE_CORE_SPICTRLR1_CSMINHIGH_Pos)


/* RSVDSPICTRLR12031 @Bits 20..31 : (unspecified) */


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Pos \

    (20UL)


#define QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Msk \

    (0xFFFUL << QSPI_CORE_CORE_SPICTRLR1_RSVDSPICTRLR12031_Pos)


/* QSPI_CORE_CORE_SPITECR: SPI Transmit Error Interrupt Clear Register */


#define QSPI_CORE_CORE_SPITECR_ResetValue \

    (0x00000000UL)


/* SPITECR @Bit 0 : Clear SPI Transmit Error interrupt. */


#define QSPI_CORE_CORE_SPITECR_SPITECR_Pos \

    (0UL)


#define QSPI_CORE_CORE_SPITECR_SPITECR_Msk \

    (0x1UL << QSPI_CORE_CORE_SPITECR_SPITECR_Pos)


/* RSVDSPITECR @Bits 1..31 : (unspecified) */


#define QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Pos \

    (1UL)


#define QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Msk \

    (0x7FFFFFFFUL << QSPI_CORE_CORE_SPITECR_RSVDSPITECR_Pos)


/* ==================================================== Struct QSPI_CORE ===================================================== */


typedef struct

{

    __IOM NRF_QSPI_CORE_CORE_Type CORE;

} NRF_QSPI_CORE_Type;


/* ================================================== Struct QSPI_SPSYNC ================================================== */


typedef struct

{

    __IOM uint32_t AUX[4];

    __IOM uint32_t DPPIMAP;

} NRF_QSPI_SPSYNC_Type;


/* QSPI_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */

  #define QSPI_SPSYNC_AUX_MaxCount   (4UL)

  #define QSPI_SPSYNC_AUX_MaxIndex   (3UL)

  #define QSPI_SPSYNC_AUX_MinIndex   (0UL)

  #define QSPI_SPSYNC_AUX_ResetValue (0x00000000UL)


/* AUX @Bits 0..31 : Auxiliary register */

  #define QSPI_SPSYNC_AUX_AUX_Pos (0UL)

  #define QSPI_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << QSPI_SPSYNC_AUX_AUX_Pos)


/* QSPI_SPSYNC_DPPIMAP: Task to handler map and DPPI subscription permissions */

  #define QSPI_SPSYNC_DPPIMAP_ResetValue (0x03204015UL)


/* VALID @Bits 0..3 : Marks this register as carrying a map the soft peripheral should apply */

  #define QSPI_SPSYNC_DPPIMAP_VALID_Pos   (0UL)

  #define QSPI_SPSYNC_DPPIMAP_VALID_Msk   (0xFUL << QSPI_SPSYNC_DPPIMAP_VALID_Pos)

  #define QSPI_SPSYNC_DPPIMAP_VALID_Valid (0x5UL)


/* ROLE0 @Bits 4..7 : Handler invoked by task entry 0 (DPPI channel 0) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_Pos    (4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE0_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE0_STOP   (0x4UL)


/* ROLE1 @Bits 8..11 : Handler invoked by task entry 1 (DPPI channel 1) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_Pos    (8UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE1_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE1_STOP   (0x4UL)


/* ROLE2 @Bits 12..15 : Handler invoked by task entry 2 (DPPI channel 2) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_Pos    (12UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE2_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE2_STOP   (0x4UL)


/* ROLE3 @Bits 16..19 : Handler invoked by task entry 3 (DPPI channel 3) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_Pos    (16UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE3_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE3_STOP   (0x4UL)


/* ROLE4 @Bits 20..23 : Handler invoked by task entry 4 (no DPPI channel) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_Pos    (20UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE4_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE4_STOP   (0x4UL)


/* ROLE5 @Bits 24..27 : Handler invoked by task entry 5 (no DPPI channel) */

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_Pos    (24UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_Msk    (0xFUL << QSPI_SPSYNC_DPPIMAP_ROLE5_Pos)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_Min    (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_Max    (0x4UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_NONE   (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_DPPI0  (0x1UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_CONFIG (0x2UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_ACTION (0x3UL)

  #define QSPI_SPSYNC_DPPIMAP_ROLE5_STOP   (0x4UL)


/* PERMIT @Bits 28..31 : Per slot permission to subscribe the DPPI channel, bit n for entry n */

  #define QSPI_SPSYNC_DPPIMAP_PERMIT_Pos (28UL)

  #define QSPI_SPSYNC_DPPIMAP_PERMIT_Msk (0xFUL << QSPI_SPSYNC_DPPIMAP_PERMIT_Pos)

  #define QSPI_SPSYNC_DPPIMAP_PERMIT_Min (0x0UL)

  #define QSPI_SPSYNC_DPPIMAP_PERMIT_Max (0xFUL)


/* ======================================================= Struct QSPI ======================================================= */


typedef struct

{

    __OM uint32_t              TASKS_START;

    __OM uint32_t              TASKS_RESET;

    __IOM uint32_t             EVENTS_CORE;

    __IOM NRF_QSPI_EVENTS_DMA_Type

                               EVENTS_DMA;

    __IOM uint32_t             EVENTS_IDLE;

    __IOM uint32_t             SHORTS;

    __IOM uint32_t             INTEN;

    __IOM uint32_t             INTENSET;

    __IOM uint32_t             INTENCLR;

    __IM uint32_t              INTPEND;

    __IOM uint32_t             ENABLE;

    __IOM NRF_QSPI_CONFIG_Type CONFIG;

    __IOM NRF_QSPI_FORMAT_Type FORMAT;

    __IOM NRF_QSPI_DMA_Type    DMA;

    __IOM NRF_QSPI_CORE_Type   CORE;

    __IOM NRF_QSPI_SPSYNC_Type SPSYNC;

} NRF_SP_QSPI_Type;


/* QSPI_TASKS_START: Start operation. */


#define QSPI_TASKS_START_ResetValue \

    (0x00000000UL)


/* TASKS_START @Bit 0 : Start operation. */


#define QSPI_TASKS_START_TASKS_START_Pos \

    (0UL)


#define QSPI_TASKS_START_TASKS_START_Msk \

    (0x1UL << QSPI_TASKS_START_TASKS_START_Pos)


#define QSPI_TASKS_START_TASKS_START_Min \

    (0x1UL)


#define QSPI_TASKS_START_TASKS_START_Max \

    (0x1UL)


#define QSPI_TASKS_START_TASKS_START_Trigger \

    (0x1UL)


/* QSPI_TASKS_RESET: Reset the QSPI */


#define QSPI_TASKS_RESET_ResetValue \

    (0x00000000UL)


/* TASKS_RESET @Bit 0 : Reset the QSPI */


#define QSPI_TASKS_RESET_TASKS_RESET_Pos \

    (0UL)


#define QSPI_TASKS_RESET_TASKS_RESET_Msk \

    (0x1UL << QSPI_TASKS_RESET_TASKS_RESET_Pos)


#define QSPI_TASKS_RESET_TASKS_RESET_Min \

    (0x1UL)


#define QSPI_TASKS_RESET_TASKS_RESET_Max \

    (0x1UL)


#define QSPI_TASKS_RESET_TASKS_RESET_Trigger \

    (0x1UL)


/* QSPI_EVENTS_CORE: Interrupt from the QSPI core */


#define QSPI_EVENTS_CORE_ResetValue \

    (0x00000000UL)


/* EVENTS_CORE @Bit 0 : Interrupt from the QSPI core */


#define QSPI_EVENTS_CORE_EVENTS_CORE_Pos \

    (0UL)


#define QSPI_EVENTS_CORE_EVENTS_CORE_Msk \

    (0x1UL << QSPI_EVENTS_CORE_EVENTS_CORE_Pos)


#define QSPI_EVENTS_CORE_EVENTS_CORE_Min \

    (0x0UL)


#define QSPI_EVENTS_CORE_EVENTS_CORE_Max \

    (0x1UL)


#define QSPI_EVENTS_CORE_EVENTS_CORE_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_CORE_EVENTS_CORE_Generated \

    (0x1UL)


/* QSPI_EVENTS_IDLE: This event signifies that the QSPI core is no longer busy */


#define QSPI_EVENTS_IDLE_ResetValue \

    (0x00000000UL)


/* EVENTS_IDLE @Bit 0 : This event signifies that the QSPI core is no longer busy */


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos \

    (0UL)


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_Msk \

    (0x1UL << QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos)


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_Min \

    (0x0UL)


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_Max \

    (0x1UL)


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_NotGenerated \

    (0x0UL)


#define QSPI_EVENTS_IDLE_EVENTS_IDLE_Generated \

    (0x1UL)


/* QSPI_SHORTS: Shortcuts between local events and tasks */


#define QSPI_SHORTS_ResetValue \

    (0x00000000UL)


/* DMA_DONE_START @Bit 0 : Shortcut between event DMA.DONE and task START */


#define QSPI_SHORTS_DMA_DONE_START_Pos \

    (0UL)


#define QSPI_SHORTS_DMA_DONE_START_Msk \

    (0x1UL << QSPI_SHORTS_DMA_DONE_START_Pos)


#define QSPI_SHORTS_DMA_DONE_START_Min \

    (0x0UL)


#define QSPI_SHORTS_DMA_DONE_START_Max \

    (0x1UL)


#define QSPI_SHORTS_DMA_DONE_START_Disabled \

    (0x0UL)


#define QSPI_SHORTS_DMA_DONE_START_Enabled \

    (0x1UL)


/* QSPI_INTEN: Enable or disable interrupt */


#define QSPI_INTEN_ResetValue \

    (0x00000000UL)


/* CORE @Bit 0 : Enable or disable interrupt for event CORE */

#define QSPI_INTEN_CORE_Pos      (0UL)


#define QSPI_INTEN_CORE_Msk \

    (0x1UL << QSPI_INTEN_CORE_Pos)


#define QSPI_INTEN_CORE_Min      (0x0UL)

#define QSPI_INTEN_CORE_Max      (0x1UL)

#define QSPI_INTEN_CORE_Disabled (0x0UL)

#define QSPI_INTEN_CORE_Enabled  (0x1UL)


/* DMADONELIST @Bit 1 : Enable or disable interrupt for event DMADONELIST */

#define QSPI_INTEN_DMADONELIST_Pos (1UL)


#define QSPI_INTEN_DMADONELIST_Msk \

    (0x1UL << QSPI_INTEN_DMADONELIST_Pos)


#define QSPI_INTEN_DMADONELIST_Min (0x0UL)

#define QSPI_INTEN_DMADONELIST_Max (0x1UL)


#define QSPI_INTEN_DMADONELIST_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMADONELIST_Enabled \

    (0x1UL)


/* DMADONELISTPART @Bit 2 : Enable or disable interrupt for event DMADONELISTPART */


#define QSPI_INTEN_DMADONELISTPART_Pos \

    (2UL)


#define QSPI_INTEN_DMADONELISTPART_Msk \

    (0x1UL << QSPI_INTEN_DMADONELISTPART_Pos)


#define QSPI_INTEN_DMADONELISTPART_Min \

    (0x0UL)


#define QSPI_INTEN_DMADONELISTPART_Max \

    (0x1UL)


#define QSPI_INTEN_DMADONELISTPART_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMADONELISTPART_Enabled \

    (0x1UL)


/* DMADONESELECTJOB @Bit 3 : Enable or disable interrupt for event DMADONESELECTJOB */


#define QSPI_INTEN_DMADONESELECTJOB_Pos \

    (3UL)


#define QSPI_INTEN_DMADONESELECTJOB_Msk \

    (0x1UL << QSPI_INTEN_DMADONESELECTJOB_Pos)


#define QSPI_INTEN_DMADONESELECTJOB_Min \

    (0x0UL)


#define QSPI_INTEN_DMADONESELECTJOB_Max \

    (0x1UL)


#define QSPI_INTEN_DMADONESELECTJOB_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMADONESELECTJOB_Enabled \

    (0x1UL)


/* DMADONEDATA @Bit 4 : Enable or disable interrupt for event DMADONEDATA */

#define QSPI_INTEN_DMADONEDATA_Pos (4UL)


#define QSPI_INTEN_DMADONEDATA_Msk \

    (0x1UL << QSPI_INTEN_DMADONEDATA_Pos)


#define QSPI_INTEN_DMADONEDATA_Min (0x0UL)

#define QSPI_INTEN_DMADONEDATA_Max (0x1UL)


#define QSPI_INTEN_DMADONEDATA_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMADONEDATA_Enabled \

    (0x1UL)


/* DMADONEJOB @Bit 5 : Enable or disable interrupt for event DMADONEJOB */

#define QSPI_INTEN_DMADONEJOB_Pos (5UL)


#define QSPI_INTEN_DMADONEJOB_Msk \

    (0x1UL << QSPI_INTEN_DMADONEJOB_Pos)


#define QSPI_INTEN_DMADONEJOB_Min (0x0UL)

#define QSPI_INTEN_DMADONEJOB_Max (0x1UL)


#define QSPI_INTEN_DMADONEJOB_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMADONEJOB_Enabled \

    (0x1UL)


/* DMAERROR @Bit 6 : Enable or disable interrupt for event DMAERROR */

#define QSPI_INTEN_DMAERROR_Pos     (6UL)


#define QSPI_INTEN_DMAERROR_Msk \

    (0x1UL << QSPI_INTEN_DMAERROR_Pos)


#define QSPI_INTEN_DMAERROR_Min     (0x0UL)

#define QSPI_INTEN_DMAERROR_Max     (0x1UL)


#define QSPI_INTEN_DMAERROR_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMAERROR_Enabled (0x1UL)


/* DMAPAUSED @Bit 7 : Enable or disable interrupt for event DMAPAUSED */

#define QSPI_INTEN_DMAPAUSED_Pos (7UL)


#define QSPI_INTEN_DMAPAUSED_Msk \

    (0x1UL << QSPI_INTEN_DMAPAUSED_Pos)


#define QSPI_INTEN_DMAPAUSED_Min (0x0UL)

#define QSPI_INTEN_DMAPAUSED_Max (0x1UL)


#define QSPI_INTEN_DMAPAUSED_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMAPAUSED_Enabled \

    (0x1UL)


/* DMARESET @Bit 8 : Enable or disable interrupt for event DMARESET */

#define QSPI_INTEN_DMARESET_Pos     (8UL)


#define QSPI_INTEN_DMARESET_Msk \

    (0x1UL << QSPI_INTEN_DMARESET_Pos)


#define QSPI_INTEN_DMARESET_Min     (0x0UL)

#define QSPI_INTEN_DMARESET_Max     (0x1UL)


#define QSPI_INTEN_DMARESET_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMARESET_Enabled (0x1UL)


/* DMADONE @Bit 9 : Enable or disable interrupt for event DMADONE */

#define QSPI_INTEN_DMADONE_Pos      (9UL)


#define QSPI_INTEN_DMADONE_Msk \

    (0x1UL << QSPI_INTEN_DMADONE_Pos)


#define QSPI_INTEN_DMADONE_Min      (0x0UL)

#define QSPI_INTEN_DMADONE_Max      (0x1UL)

#define QSPI_INTEN_DMADONE_Disabled (0x0UL)

#define QSPI_INTEN_DMADONE_Enabled  (0x1UL)


/* DMATXUNEXPECTEDIDLE @Bit 10 : Enable or disable interrupt for event DMATXUNEXPECTEDIDLE */


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos \

    (10UL)


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos)


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Enabled \

    (0x1UL)


/* DMAINTERNALBUSERROR @Bit 11 : Enable or disable interrupt for event DMAINTERNALBUSERROR */


#define QSPI_INTEN_DMAINTERNALBUSERROR_Pos \

    (11UL)


#define QSPI_INTEN_DMAINTERNALBUSERROR_Msk \

    (0x1UL << QSPI_INTEN_DMAINTERNALBUSERROR_Pos)


#define QSPI_INTEN_DMAINTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_INTEN_DMAINTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_INTEN_DMAINTERNALBUSERROR_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMAINTERNALBUSERROR_Enabled \

    (0x1UL)


/* DMAABORTED @Bit 12 : Enable or disable interrupt for event DMAABORTED */

#define QSPI_INTEN_DMAABORTED_Pos (12UL)


#define QSPI_INTEN_DMAABORTED_Msk \

    (0x1UL << QSPI_INTEN_DMAABORTED_Pos)


#define QSPI_INTEN_DMAABORTED_Min (0x0UL)

#define QSPI_INTEN_DMAABORTED_Max (0x1UL)


#define QSPI_INTEN_DMAABORTED_Disabled \

    (0x0UL)


#define QSPI_INTEN_DMAABORTED_Enabled \

    (0x1UL)


/* IDLE @Bit 13 : Enable or disable interrupt for event IDLE */

#define QSPI_INTEN_IDLE_Pos      (13UL)


#define QSPI_INTEN_IDLE_Msk \

    (0x1UL << QSPI_INTEN_IDLE_Pos)


#define QSPI_INTEN_IDLE_Min      (0x0UL)

#define QSPI_INTEN_IDLE_Max      (0x1UL)

#define QSPI_INTEN_IDLE_Disabled (0x0UL)

#define QSPI_INTEN_IDLE_Enabled  (0x1UL)


/* QSPI_INTENSET: Enable interrupt */


#define QSPI_INTENSET_ResetValue \

    (0x00000000UL)


/* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */

#define QSPI_INTENSET_CORE_Pos      (0UL)


#define QSPI_INTENSET_CORE_Msk \

    (0x1UL << QSPI_INTENSET_CORE_Pos)


#define QSPI_INTENSET_CORE_Min      (0x0UL)

#define QSPI_INTENSET_CORE_Max      (0x1UL)

#define QSPI_INTENSET_CORE_Set      (0x1UL)

#define QSPI_INTENSET_CORE_Disabled (0x0UL)

#define QSPI_INTENSET_CORE_Enabled  (0x1UL)


/* DMADONELIST @Bit 1 : Write '1' to enable interrupt for event DMADONELIST */

#define QSPI_INTENSET_DMADONELIST_Pos (1UL)


#define QSPI_INTENSET_DMADONELIST_Msk \

    (0x1UL << QSPI_INTENSET_DMADONELIST_Pos)


#define QSPI_INTENSET_DMADONELIST_Min \

    (0x0UL)


#define QSPI_INTENSET_DMADONELIST_Max \

    (0x1UL)


#define QSPI_INTENSET_DMADONELIST_Set \

    (0x1UL)


#define QSPI_INTENSET_DMADONELIST_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONELIST_Enabled \

    (0x1UL)


/* DMADONELISTPART @Bit 2 : Write '1' to enable interrupt for event DMADONELISTPART */


#define QSPI_INTENSET_DMADONELISTPART_Pos \

    (2UL)


#define QSPI_INTENSET_DMADONELISTPART_Msk \

    (0x1UL << QSPI_INTENSET_DMADONELISTPART_Pos)


#define QSPI_INTENSET_DMADONELISTPART_Min \

    (0x0UL)


#define QSPI_INTENSET_DMADONELISTPART_Max \

    (0x1UL)


#define QSPI_INTENSET_DMADONELISTPART_Set \

    (0x1UL)


#define QSPI_INTENSET_DMADONELISTPART_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONELISTPART_Enabled \

    (0x1UL)


/* DMADONESELECTJOB @Bit 3 : Write '1' to enable interrupt for event DMADONESELECTJOB */


#define QSPI_INTENSET_DMADONESELECTJOB_Pos \

    (3UL)


#define QSPI_INTENSET_DMADONESELECTJOB_Msk \

    (0x1UL << QSPI_INTENSET_DMADONESELECTJOB_Pos)


#define QSPI_INTENSET_DMADONESELECTJOB_Min \

    (0x0UL)


#define QSPI_INTENSET_DMADONESELECTJOB_Max \

    (0x1UL)


#define QSPI_INTENSET_DMADONESELECTJOB_Set \

    (0x1UL)


#define QSPI_INTENSET_DMADONESELECTJOB_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONESELECTJOB_Enabled \

    (0x1UL)


/* DMADONEDATA @Bit 4 : Write '1' to enable interrupt for event DMADONEDATA */

#define QSPI_INTENSET_DMADONEDATA_Pos (4UL)


#define QSPI_INTENSET_DMADONEDATA_Msk \

    (0x1UL << QSPI_INTENSET_DMADONEDATA_Pos)


#define QSPI_INTENSET_DMADONEDATA_Min \

    (0x0UL)


#define QSPI_INTENSET_DMADONEDATA_Max \

    (0x1UL)


#define QSPI_INTENSET_DMADONEDATA_Set \

    (0x1UL)


#define QSPI_INTENSET_DMADONEDATA_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONEDATA_Enabled \

    (0x1UL)


/* DMADONEJOB @Bit 5 : Write '1' to enable interrupt for event DMADONEJOB */

#define QSPI_INTENSET_DMADONEJOB_Pos (5UL)


#define QSPI_INTENSET_DMADONEJOB_Msk \

    (0x1UL << QSPI_INTENSET_DMADONEJOB_Pos)


#define QSPI_INTENSET_DMADONEJOB_Min \

    (0x0UL)


#define QSPI_INTENSET_DMADONEJOB_Max \

    (0x1UL)


#define QSPI_INTENSET_DMADONEJOB_Set \

    (0x1UL)


#define QSPI_INTENSET_DMADONEJOB_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONEJOB_Enabled \

    (0x1UL)


/* DMAERROR @Bit 6 : Write '1' to enable interrupt for event DMAERROR */

#define QSPI_INTENSET_DMAERROR_Pos (6UL)


#define QSPI_INTENSET_DMAERROR_Msk \

    (0x1UL << QSPI_INTENSET_DMAERROR_Pos)


#define QSPI_INTENSET_DMAERROR_Min (0x0UL)

#define QSPI_INTENSET_DMAERROR_Max (0x1UL)

#define QSPI_INTENSET_DMAERROR_Set (0x1UL)


#define QSPI_INTENSET_DMAERROR_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMAERROR_Enabled \

    (0x1UL)


/* DMAPAUSED @Bit 7 : Write '1' to enable interrupt for event DMAPAUSED */

#define QSPI_INTENSET_DMAPAUSED_Pos (7UL)


#define QSPI_INTENSET_DMAPAUSED_Msk \

    (0x1UL << QSPI_INTENSET_DMAPAUSED_Pos)


#define QSPI_INTENSET_DMAPAUSED_Min (0x0UL)

#define QSPI_INTENSET_DMAPAUSED_Max (0x1UL)

#define QSPI_INTENSET_DMAPAUSED_Set (0x1UL)


#define QSPI_INTENSET_DMAPAUSED_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMAPAUSED_Enabled \

    (0x1UL)


/* DMARESET @Bit 8 : Write '1' to enable interrupt for event DMARESET */

#define QSPI_INTENSET_DMARESET_Pos (8UL)


#define QSPI_INTENSET_DMARESET_Msk \

    (0x1UL << QSPI_INTENSET_DMARESET_Pos)


#define QSPI_INTENSET_DMARESET_Min (0x0UL)

#define QSPI_INTENSET_DMARESET_Max (0x1UL)

#define QSPI_INTENSET_DMARESET_Set (0x1UL)


#define QSPI_INTENSET_DMARESET_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMARESET_Enabled \

    (0x1UL)


/* DMADONE @Bit 9 : Write '1' to enable interrupt for event DMADONE */

#define QSPI_INTENSET_DMADONE_Pos (9UL)


#define QSPI_INTENSET_DMADONE_Msk \

    (0x1UL << QSPI_INTENSET_DMADONE_Pos)


#define QSPI_INTENSET_DMADONE_Min (0x0UL)

#define QSPI_INTENSET_DMADONE_Max (0x1UL)

#define QSPI_INTENSET_DMADONE_Set (0x1UL)


#define QSPI_INTENSET_DMADONE_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMADONE_Enabled \

    (0x1UL)


/* DMATXUNEXPECTEDIDLE @Bit 10 : Write '1' to enable interrupt for event DMATXUNEXPECTEDIDLE */


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos \

    (10UL)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Set \

    (0x1UL)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Enabled \

    (0x1UL)


/* DMAINTERNALBUSERROR @Bit 11 : Write '1' to enable interrupt for event DMAINTERNALBUSERROR */


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Pos \

    (11UL)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Msk \

    (0x1UL << QSPI_INTENSET_DMAINTERNALBUSERROR_Pos)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Set \

    (0x1UL)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMAINTERNALBUSERROR_Enabled \

    (0x1UL)


/* DMAABORTED @Bit 12 : Write '1' to enable interrupt for event DMAABORTED */

#define QSPI_INTENSET_DMAABORTED_Pos (12UL)


#define QSPI_INTENSET_DMAABORTED_Msk \

    (0x1UL << QSPI_INTENSET_DMAABORTED_Pos)


#define QSPI_INTENSET_DMAABORTED_Min \

    (0x0UL)


#define QSPI_INTENSET_DMAABORTED_Max \

    (0x1UL)


#define QSPI_INTENSET_DMAABORTED_Set \

    (0x1UL)


#define QSPI_INTENSET_DMAABORTED_Disabled \

    (0x0UL)


#define QSPI_INTENSET_DMAABORTED_Enabled \

    (0x1UL)


/* IDLE @Bit 13 : Write '1' to enable interrupt for event IDLE */

#define QSPI_INTENSET_IDLE_Pos      (13UL)


#define QSPI_INTENSET_IDLE_Msk \

    (0x1UL << QSPI_INTENSET_IDLE_Pos)


#define QSPI_INTENSET_IDLE_Min      (0x0UL)

#define QSPI_INTENSET_IDLE_Max      (0x1UL)

#define QSPI_INTENSET_IDLE_Set      (0x1UL)

#define QSPI_INTENSET_IDLE_Disabled (0x0UL)

#define QSPI_INTENSET_IDLE_Enabled  (0x1UL)


/* QSPI_INTENCLR: Disable interrupt */


#define QSPI_INTENCLR_ResetValue \

    (0x00000000UL)


/* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */

#define QSPI_INTENCLR_CORE_Pos      (0UL)


#define QSPI_INTENCLR_CORE_Msk \

    (0x1UL << QSPI_INTENCLR_CORE_Pos)


#define QSPI_INTENCLR_CORE_Min      (0x0UL)

#define QSPI_INTENCLR_CORE_Max      (0x1UL)

#define QSPI_INTENCLR_CORE_Clear    (0x1UL)

#define QSPI_INTENCLR_CORE_Disabled (0x0UL)

#define QSPI_INTENCLR_CORE_Enabled  (0x1UL)


/* DMADONELIST @Bit 1 : Write '1' to disable interrupt for event DMADONELIST */

#define QSPI_INTENCLR_DMADONELIST_Pos (1UL)


#define QSPI_INTENCLR_DMADONELIST_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONELIST_Pos)


#define QSPI_INTENCLR_DMADONELIST_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMADONELIST_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMADONELIST_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMADONELIST_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONELIST_Enabled \

    (0x1UL)


/* DMADONELISTPART @Bit 2 : Write '1' to disable interrupt for event DMADONELISTPART */


#define QSPI_INTENCLR_DMADONELISTPART_Pos \

    (2UL)


#define QSPI_INTENCLR_DMADONELISTPART_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONELISTPART_Pos)


#define QSPI_INTENCLR_DMADONELISTPART_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMADONELISTPART_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMADONELISTPART_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMADONELISTPART_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONELISTPART_Enabled \

    (0x1UL)


/* DMADONESELECTJOB @Bit 3 : Write '1' to disable interrupt for event DMADONESELECTJOB */


#define QSPI_INTENCLR_DMADONESELECTJOB_Pos \

    (3UL)


#define QSPI_INTENCLR_DMADONESELECTJOB_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONESELECTJOB_Pos)


#define QSPI_INTENCLR_DMADONESELECTJOB_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMADONESELECTJOB_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMADONESELECTJOB_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMADONESELECTJOB_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONESELECTJOB_Enabled \

    (0x1UL)


/* DMADONEDATA @Bit 4 : Write '1' to disable interrupt for event DMADONEDATA */

#define QSPI_INTENCLR_DMADONEDATA_Pos (4UL)


#define QSPI_INTENCLR_DMADONEDATA_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONEDATA_Pos)


#define QSPI_INTENCLR_DMADONEDATA_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMADONEDATA_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMADONEDATA_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMADONEDATA_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONEDATA_Enabled \

    (0x1UL)


/* DMADONEJOB @Bit 5 : Write '1' to disable interrupt for event DMADONEJOB */

#define QSPI_INTENCLR_DMADONEJOB_Pos (5UL)


#define QSPI_INTENCLR_DMADONEJOB_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONEJOB_Pos)


#define QSPI_INTENCLR_DMADONEJOB_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMADONEJOB_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMADONEJOB_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMADONEJOB_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONEJOB_Enabled \

    (0x1UL)


/* DMAERROR @Bit 6 : Write '1' to disable interrupt for event DMAERROR */

#define QSPI_INTENCLR_DMAERROR_Pos (6UL)


#define QSPI_INTENCLR_DMAERROR_Msk \

    (0x1UL << QSPI_INTENCLR_DMAERROR_Pos)


#define QSPI_INTENCLR_DMAERROR_Min (0x0UL)

#define QSPI_INTENCLR_DMAERROR_Max (0x1UL)


#define QSPI_INTENCLR_DMAERROR_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMAERROR_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMAERROR_Enabled \

    (0x1UL)


/* DMAPAUSED @Bit 7 : Write '1' to disable interrupt for event DMAPAUSED */

#define QSPI_INTENCLR_DMAPAUSED_Pos (7UL)


#define QSPI_INTENCLR_DMAPAUSED_Msk \

    (0x1UL << QSPI_INTENCLR_DMAPAUSED_Pos)


#define QSPI_INTENCLR_DMAPAUSED_Min (0x0UL)

#define QSPI_INTENCLR_DMAPAUSED_Max (0x1UL)


#define QSPI_INTENCLR_DMAPAUSED_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMAPAUSED_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMAPAUSED_Enabled \

    (0x1UL)


/* DMARESET @Bit 8 : Write '1' to disable interrupt for event DMARESET */

#define QSPI_INTENCLR_DMARESET_Pos (8UL)


#define QSPI_INTENCLR_DMARESET_Msk \

    (0x1UL << QSPI_INTENCLR_DMARESET_Pos)


#define QSPI_INTENCLR_DMARESET_Min (0x0UL)

#define QSPI_INTENCLR_DMARESET_Max (0x1UL)


#define QSPI_INTENCLR_DMARESET_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMARESET_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMARESET_Enabled \

    (0x1UL)


/* DMADONE @Bit 9 : Write '1' to disable interrupt for event DMADONE */

#define QSPI_INTENCLR_DMADONE_Pos   (9UL)


#define QSPI_INTENCLR_DMADONE_Msk \

    (0x1UL << QSPI_INTENCLR_DMADONE_Pos)


#define QSPI_INTENCLR_DMADONE_Min   (0x0UL)

#define QSPI_INTENCLR_DMADONE_Max   (0x1UL)

#define QSPI_INTENCLR_DMADONE_Clear (0x1UL)


#define QSPI_INTENCLR_DMADONE_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMADONE_Enabled \

    (0x1UL)


/* DMATXUNEXPECTEDIDLE @Bit 10 : Write '1' to disable interrupt for event DMATXUNEXPECTEDIDLE */


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos \

    (10UL)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Enabled \

    (0x1UL)


/* DMAINTERNALBUSERROR @Bit 11 : Write '1' to disable interrupt for event DMAINTERNALBUSERROR */


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos \

    (11UL)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Msk \

    (0x1UL << QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMAINTERNALBUSERROR_Enabled \

    (0x1UL)


/* DMAABORTED @Bit 12 : Write '1' to disable interrupt for event DMAABORTED */

#define QSPI_INTENCLR_DMAABORTED_Pos (12UL)


#define QSPI_INTENCLR_DMAABORTED_Msk \

    (0x1UL << QSPI_INTENCLR_DMAABORTED_Pos)


#define QSPI_INTENCLR_DMAABORTED_Min \

    (0x0UL)


#define QSPI_INTENCLR_DMAABORTED_Max \

    (0x1UL)


#define QSPI_INTENCLR_DMAABORTED_Clear \

    (0x1UL)


#define QSPI_INTENCLR_DMAABORTED_Disabled \

    (0x0UL)


#define QSPI_INTENCLR_DMAABORTED_Enabled \

    (0x1UL)


/* IDLE @Bit 13 : Write '1' to disable interrupt for event IDLE */

#define QSPI_INTENCLR_IDLE_Pos      (13UL)


#define QSPI_INTENCLR_IDLE_Msk \

    (0x1UL << QSPI_INTENCLR_IDLE_Pos)


#define QSPI_INTENCLR_IDLE_Min      (0x0UL)

#define QSPI_INTENCLR_IDLE_Max      (0x1UL)

#define QSPI_INTENCLR_IDLE_Clear    (0x1UL)

#define QSPI_INTENCLR_IDLE_Disabled (0x0UL)

#define QSPI_INTENCLR_IDLE_Enabled  (0x1UL)


/* QSPI_INTPEND: Pending interrupts */


#define QSPI_INTPEND_ResetValue \

    (0x00000000UL)


/* CORE @Bit 0 : Read pending status of interrupt for event CORE */

#define QSPI_INTPEND_CORE_Pos     (0UL)


#define QSPI_INTPEND_CORE_Msk \

    (0x1UL << QSPI_INTPEND_CORE_Pos)


#define QSPI_INTPEND_CORE_Min     (0x0UL)

#define QSPI_INTPEND_CORE_Max     (0x1UL)


#define QSPI_INTPEND_CORE_NotPending \

    (0x0UL)


#define QSPI_INTPEND_CORE_Pending (0x1UL)


/* DMADONELIST @Bit 1 : Read pending status of interrupt for event DMADONELIST */

#define QSPI_INTPEND_DMADONELIST_Pos (1UL)


#define QSPI_INTPEND_DMADONELIST_Msk \

    (0x1UL << QSPI_INTPEND_DMADONELIST_Pos)


#define QSPI_INTPEND_DMADONELIST_Min \

    (0x0UL)


#define QSPI_INTPEND_DMADONELIST_Max \

    (0x1UL)


#define QSPI_INTPEND_DMADONELIST_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONELIST_Pending \

    (0x1UL)


/* DMADONELISTPART @Bit 2 : Read pending status of interrupt for event DMADONELISTPART */


#define QSPI_INTPEND_DMADONELISTPART_Pos \

    (2UL)


#define QSPI_INTPEND_DMADONELISTPART_Msk \

    (0x1UL << QSPI_INTPEND_DMADONELISTPART_Pos)


#define QSPI_INTPEND_DMADONELISTPART_Min \

    (0x0UL)


#define QSPI_INTPEND_DMADONELISTPART_Max \

    (0x1UL)


#define QSPI_INTPEND_DMADONELISTPART_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONELISTPART_Pending \

    (0x1UL)


/* DMADONESELECTJOB @Bit 3 : Read pending status of interrupt for event DMADONESELECTJOB */


#define QSPI_INTPEND_DMADONESELECTJOB_Pos \

    (3UL)


#define QSPI_INTPEND_DMADONESELECTJOB_Msk \

    (0x1UL << QSPI_INTPEND_DMADONESELECTJOB_Pos)


#define QSPI_INTPEND_DMADONESELECTJOB_Min \

    (0x0UL)


#define QSPI_INTPEND_DMADONESELECTJOB_Max \

    (0x1UL)


#define QSPI_INTPEND_DMADONESELECTJOB_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONESELECTJOB_Pending \

    (0x1UL)


/* DMADONEDATA @Bit 4 : Read pending status of interrupt for event DMADONEDATA */

#define QSPI_INTPEND_DMADONEDATA_Pos (4UL)


#define QSPI_INTPEND_DMADONEDATA_Msk \

    (0x1UL << QSPI_INTPEND_DMADONEDATA_Pos)


#define QSPI_INTPEND_DMADONEDATA_Min \

    (0x0UL)


#define QSPI_INTPEND_DMADONEDATA_Max \

    (0x1UL)


#define QSPI_INTPEND_DMADONEDATA_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONEDATA_Pending \

    (0x1UL)


/* DMADONEJOB @Bit 5 : Read pending status of interrupt for event DMADONEJOB */

#define QSPI_INTPEND_DMADONEJOB_Pos (5UL)


#define QSPI_INTPEND_DMADONEJOB_Msk \

    (0x1UL << QSPI_INTPEND_DMADONEJOB_Pos)


#define QSPI_INTPEND_DMADONEJOB_Min (0x0UL)

#define QSPI_INTPEND_DMADONEJOB_Max (0x1UL)


#define QSPI_INTPEND_DMADONEJOB_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONEJOB_Pending \

    (0x1UL)


/* DMAERROR @Bit 6 : Read pending status of interrupt for event DMAERROR */

#define QSPI_INTPEND_DMAERROR_Pos (6UL)


#define QSPI_INTPEND_DMAERROR_Msk \

    (0x1UL << QSPI_INTPEND_DMAERROR_Pos)


#define QSPI_INTPEND_DMAERROR_Min (0x0UL)

#define QSPI_INTPEND_DMAERROR_Max (0x1UL)


#define QSPI_INTPEND_DMAERROR_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMAERROR_Pending \

    (0x1UL)


/* DMAPAUSED @Bit 7 : Read pending status of interrupt for event DMAPAUSED */

#define QSPI_INTPEND_DMAPAUSED_Pos (7UL)


#define QSPI_INTPEND_DMAPAUSED_Msk \

    (0x1UL << QSPI_INTPEND_DMAPAUSED_Pos)


#define QSPI_INTPEND_DMAPAUSED_Min (0x0UL)

#define QSPI_INTPEND_DMAPAUSED_Max (0x1UL)


#define QSPI_INTPEND_DMAPAUSED_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMAPAUSED_Pending \

    (0x1UL)


/* DMARESET @Bit 8 : Read pending status of interrupt for event DMARESET */

#define QSPI_INTPEND_DMARESET_Pos (8UL)


#define QSPI_INTPEND_DMARESET_Msk \

    (0x1UL << QSPI_INTPEND_DMARESET_Pos)


#define QSPI_INTPEND_DMARESET_Min (0x0UL)

#define QSPI_INTPEND_DMARESET_Max (0x1UL)


#define QSPI_INTPEND_DMARESET_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMARESET_Pending \

    (0x1UL)


/* DMADONE @Bit 9 : Read pending status of interrupt for event DMADONE */

#define QSPI_INTPEND_DMADONE_Pos (9UL)


#define QSPI_INTPEND_DMADONE_Msk \

    (0x1UL << QSPI_INTPEND_DMADONE_Pos)


#define QSPI_INTPEND_DMADONE_Min (0x0UL)

#define QSPI_INTPEND_DMADONE_Max (0x1UL)


#define QSPI_INTPEND_DMADONE_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMADONE_Pending \

    (0x1UL)


/* DMATXUNEXPECTEDIDLE @Bit 10 : Read pending status of interrupt for event DMATXUNEXPECTEDIDLE */


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos \

    (10UL)


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Msk \

    (0x1UL << QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos)


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Min \

    (0x0UL)


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Max \

    (0x1UL)


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pending \

    (0x1UL)


/* DMAINTERNALBUSERROR @Bit 11 : Read pending status of interrupt for event DMAINTERNALBUSERROR */


#define QSPI_INTPEND_DMAINTERNALBUSERROR_Pos \

    (11UL)


#define QSPI_INTPEND_DMAINTERNALBUSERROR_Msk \

    (0x1UL << QSPI_INTPEND_DMAINTERNALBUSERROR_Pos)


#define QSPI_INTPEND_DMAINTERNALBUSERROR_Min \

    (0x0UL)


#define QSPI_INTPEND_DMAINTERNALBUSERROR_Max \

    (0x1UL)


#define QSPI_INTPEND_DMAINTERNALBUSERROR_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMAINTERNALBUSERROR_Pending \

    (0x1UL)


/* DMAABORTED @Bit 12 : Read pending status of interrupt for event DMAABORTED */

#define QSPI_INTPEND_DMAABORTED_Pos (12UL)


#define QSPI_INTPEND_DMAABORTED_Msk \

    (0x1UL << QSPI_INTPEND_DMAABORTED_Pos)


#define QSPI_INTPEND_DMAABORTED_Min (0x0UL)

#define QSPI_INTPEND_DMAABORTED_Max (0x1UL)


#define QSPI_INTPEND_DMAABORTED_NotPending \

    (0x0UL)


#define QSPI_INTPEND_DMAABORTED_Pending \

    (0x1UL)


/* IDLE @Bit 13 : Read pending status of interrupt for event IDLE */

#define QSPI_INTPEND_IDLE_Pos     (13UL)


#define QSPI_INTPEND_IDLE_Msk \

    (0x1UL << QSPI_INTPEND_IDLE_Pos)


#define QSPI_INTPEND_IDLE_Min     (0x0UL)

#define QSPI_INTPEND_IDLE_Max     (0x1UL)


#define QSPI_INTPEND_IDLE_NotPending \

    (0x0UL)


#define QSPI_INTPEND_IDLE_Pending (0x1UL)


/* QSPI_ENABLE: Enables the QSPI This requests clock for the IP core */


#define QSPI_ENABLE_ResetValue \

    (0x00000000UL)


/* ENABLE @Bit 0 : Enable the QSPI */

#define QSPI_ENABLE_ENABLE_Pos (0UL)


#define QSPI_ENABLE_ENABLE_Msk \

    (0x1UL << QSPI_ENABLE_ENABLE_Pos)


#endif


#endif // NRF_SP_QSPI_H__

NRF_QSPI_CONFIG_Type::TXBURSTLENGTH
__IOM uint32_t TXBURSTLENGTH
Definition nrf_sp_qspi.h:315

NRF_QSPI_CONFIG_Type::RXTRANSFERLENGTH
__IOM uint32_t RXTRANSFERLENGTH
Definition nrf_sp_qspi.h:317

NRF_QSPI_CONFIG_Type::RXBURSTLENGTH
__IOM uint32_t RXBURSTLENGTH
Definition nrf_sp_qspi.h:316

NRF_QSPI_CONFIG_Type::STOPON
__IOM uint32_t STOPON
Definition nrf_sp_qspi.h:318

NRF_QSPI_CONFIG_Type::AXIMODE
__IOM uint32_t AXIMODE
Definition nrf_sp_qspi.h:320

NRF_QSPI_CONFIG_Type
CONFIG [QSPI_CONFIG] (unspecified).
Definition nrf_sp_qspi.h:314

NRF_QSPI_CORE_CORE_Type::RXFLR
__IOM uint32_t RXFLR
Definition nrf_sp_qspi.h:726

NRF_QSPI_CORE_CORE_Type::ICR
__IOM uint32_t ICR
Definition nrf_sp_qspi.h:735

NRF_QSPI_CORE_CORE_Type::DMARDLR
__IOM uint32_t DMARDLR
Definition nrf_sp_qspi.h:738

NRF_QSPI_CORE_CORE_Type::BAUDR
__IOM uint32_t BAUDR
Definition nrf_sp_qspi.h:722

NRF_QSPI_CORE_CORE_Type::RXFTLR
__IOM uint32_t RXFTLR
Definition nrf_sp_qspi.h:724

NRF_QSPI_CORE_CORE_Type::RXSAMPLEDELAY
__IOM uint32_t RXSAMPLEDELAY
Definition nrf_sp_qspi.h:742

NRF_QSPI_CORE_CORE_Type::DMACR
__IOM uint32_t DMACR
Definition nrf_sp_qspi.h:736

NRF_QSPI_CORE_CORE_Type::DR
__IOM uint32_t DR[36]
Definition nrf_sp_qspi.h:741

NRF_QSPI_CORE_CORE_Type::IMR
__IOM uint32_t IMR
Definition nrf_sp_qspi.h:728

NRF_QSPI_CORE_CORE_Type::CTRLR0
__IOM uint32_t CTRLR0
Definition nrf_sp_qspi.h:717

NRF_QSPI_CORE_CORE_Type::SQSPIENR
__IOM uint32_t SQSPIENR
Definition nrf_sp_qspi.h:719

NRF_QSPI_CORE_CORE_Type::SER
__IOM uint32_t SER
Definition nrf_sp_qspi.h:721

NRF_QSPI_CORE_CORE_Type::TXFLR
__IOM uint32_t TXFLR
Definition nrf_sp_qspi.h:725

NRF_QSPI_CORE_CORE_Type::RISR
__IOM uint32_t RISR
Definition nrf_sp_qspi.h:730

NRF_QSPI_CORE_CORE_Type::SQSPICVERSIONID
__IOM uint32_t SQSPICVERSIONID
Definition nrf_sp_qspi.h:740

NRF_QSPI_CORE_CORE_Type::ISR
__IOM uint32_t ISR
Definition nrf_sp_qspi.h:729

NRF_QSPI_CORE_CORE_Type::DMATDLR
__IOM uint32_t DMATDLR
Definition nrf_sp_qspi.h:737

NRF_QSPI_CORE_CORE_Type::SPICTRLR1
__IOM uint32_t SPICTRLR1
Definition nrf_sp_qspi.h:744

NRF_QSPI_CORE_CORE_Type::IDR
__IOM uint32_t IDR
Definition nrf_sp_qspi.h:739

NRF_QSPI_CORE_CORE_Type::MSTICR
__IOM uint32_t MSTICR
Definition nrf_sp_qspi.h:734

NRF_QSPI_CORE_CORE_Type::TXFTLR
__IOM uint32_t TXFTLR
Definition nrf_sp_qspi.h:723

NRF_QSPI_CORE_CORE_Type::TXEICR
__IOM uint32_t TXEICR
Definition nrf_sp_qspi.h:731

NRF_QSPI_CORE_CORE_Type::RXOICR
__IOM uint32_t RXOICR
Definition nrf_sp_qspi.h:732

NRF_QSPI_CORE_CORE_Type::SPITECR
__IOM uint32_t SPITECR
Definition nrf_sp_qspi.h:745

NRF_QSPI_CORE_CORE_Type::MWCR
__IOM uint32_t MWCR
Definition nrf_sp_qspi.h:720

NRF_QSPI_CORE_CORE_Type::SPICTRLR0
__IOM uint32_t SPICTRLR0
Definition nrf_sp_qspi.h:743

NRF_QSPI_CORE_CORE_Type::RXUICR
__IOM uint32_t RXUICR
Definition nrf_sp_qspi.h:733

NRF_QSPI_CORE_CORE_Type::CTRLR1
__IOM uint32_t CTRLR1
Definition nrf_sp_qspi.h:718

NRF_QSPI_CORE_CORE_Type::SR
__IOM uint32_t SR
Definition nrf_sp_qspi.h:727

NRF_QSPI_CORE_CORE_Type
CORE [QSPI_CORE_CORE] (unspecified).
Definition nrf_sp_qspi.h:716

NRF_QSPI_CORE_Type::CORE
__IOM NRF_QSPI_CORE_CORE_Type CORE
Definition nrf_sp_qspi.h:2454

NRF_QSPI_CORE_Type
CORE [QSPI_CORE] (unspecified).
Definition nrf_sp_qspi.h:2453

NRF_QSPI_DMA_CONFIG_Type::BUFFERFILL
__IOM uint32_t BUFFERFILL
Definition nrf_sp_qspi.h:658

NRF_QSPI_DMA_CONFIG_Type::LISTPARTTHRESH
__IOM uint32_t LISTPARTTHRESH
Definition nrf_sp_qspi.h:661

NRF_QSPI_DMA_CONFIG_Type::LISTPTR
__IOM uint32_t LISTPTR
Definition nrf_sp_qspi.h:660

NRF_QSPI_DMA_CONFIG_Type
CONFIG [QSPI_DMA_CONFIG] General config registers.
Definition nrf_sp_qspi.h:657

NRF_QSPI_DMA_STATUS_Type::ACTIVE
__IM uint32_t ACTIVE
Definition nrf_sp_qspi.h:522

NRF_QSPI_DMA_STATUS_Type::FIFO
__IM uint32_t FIFO
Definition nrf_sp_qspi.h:521

NRF_QSPI_DMA_STATUS_Type::ADDRESS
__IM uint32_t ADDRESS
Definition nrf_sp_qspi.h:518

NRF_QSPI_DMA_STATUS_Type::BYTECOUNT
__IM uint32_t BYTECOUNT
Definition nrf_sp_qspi.h:515

NRF_QSPI_DMA_STATUS_Type::BUSERROR
__IM uint32_t BUSERROR
Definition nrf_sp_qspi.h:520

NRF_QSPI_DMA_STATUS_Type::ATTRIBUTE
__IM uint32_t ATTRIBUTE
Definition nrf_sp_qspi.h:517

NRF_QSPI_DMA_STATUS_Type::JOBCOUNT
__IM uint32_t JOBCOUNT
Definition nrf_sp_qspi.h:519

NRF_QSPI_DMA_STATUS_Type
STATUS [QSPI_DMA_STATUS] EasyVDMA status registers.
Definition nrf_sp_qspi.h:514

NRF_QSPI_DMA_Type::CONFIG
__IOM NRF_QSPI_DMA_CONFIG_Type CONFIG
Definition nrf_sp_qspi.h:708

NRF_QSPI_DMA_Type::STATUS
__IOM NRF_QSPI_DMA_STATUS_Type STATUS
Definition nrf_sp_qspi.h:707

NRF_QSPI_DMA_Type
DMA [QSPI_DMA] (unspecified).
Definition nrf_sp_qspi.h:706

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type::SELECTJOB
__IOM uint32_t SELECTJOB
Definition nrf_sp_qspi.h:27

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type::DATA
__IOM uint32_t DATA
Definition nrf_sp_qspi.h:29

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type::JOB
__IOM uint32_t JOB
Definition nrf_sp_qspi.h:32

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type::LIST
__IOM uint32_t LIST
Definition nrf_sp_qspi.h:24

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type::LISTPART
__IOM uint32_t LISTPART
Definition nrf_sp_qspi.h:25

NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type
EVENTS_DONE [QSPI_EVENTS_DMA_EVENTS_DONE] Peripheral events.
Definition nrf_sp_qspi.h:23

NRF_QSPI_EVENTS_DMA_Type::DONE
__IOM uint32_t DONE
Definition nrf_sp_qspi.h:147

NRF_QSPI_EVENTS_DMA_Type::PAUSED
__IOM uint32_t PAUSED
Definition nrf_sp_qspi.h:145

NRF_QSPI_EVENTS_DMA_Type::RESET
__IOM uint32_t RESET
Definition nrf_sp_qspi.h:146

NRF_QSPI_EVENTS_DMA_Type::EVENTS_DONE
__IOM NRF_QSPI_EVENTS_DMA_EVENTS_DONE_Type EVENTS_DONE
Definition nrf_sp_qspi.h:143

NRF_QSPI_EVENTS_DMA_Type::ERROR
__IOM uint32_t ERROR
Definition nrf_sp_qspi.h:144

NRF_QSPI_EVENTS_DMA_Type::TXUNEXPECTEDIDLE
__IOM uint32_t TXUNEXPECTEDIDLE
Definition nrf_sp_qspi.h:148

NRF_QSPI_EVENTS_DMA_Type::ABORTED
__IOM uint32_t ABORTED
Definition nrf_sp_qspi.h:159

NRF_QSPI_EVENTS_DMA_Type::INTERNALBUSERROR
__IOM uint32_t INTERNALBUSERROR
Definition nrf_sp_qspi.h:153

NRF_QSPI_EVENTS_DMA_Type
EVENTS_DMA [QSPI_EVENTS_DMA] Peripheral events.
Definition nrf_sp_qspi.h:141

NRF_QSPI_FORMAT_Type::DFS
__IOM uint32_t DFS
Definition nrf_sp_qspi.h:450

NRF_QSPI_FORMAT_Type::CILEN
__IOM uint32_t CILEN
Definition nrf_sp_qspi.h:453

NRF_QSPI_FORMAT_Type::PIXELS
__IOM uint32_t PIXELS
Definition nrf_sp_qspi.h:452

NRF_QSPI_FORMAT_Type::BPP
__IOM uint32_t BPP
Definition nrf_sp_qspi.h:451

NRF_QSPI_FORMAT_Type::BITORDER
__IOM uint32_t BITORDER
Definition nrf_sp_qspi.h:454

NRF_QSPI_FORMAT_Type
FORMAT [QSPI_FORMAT] (unspecified).
Definition nrf_sp_qspi.h:449

NRF_QSPI_SPSYNC_Type::DPPIMAP
__IOM uint32_t DPPIMAP
Definition nrf_sp_qspi.h:2464

NRF_QSPI_SPSYNC_Type::AUX
__IOM uint32_t AUX[4]
Definition nrf_sp_qspi.h:2463

NRF_QSPI_SPSYNC_Type
SPSYNC [QSPI_SPSYNC] Registers used to acknowledge API function calls.
Definition nrf_sp_qspi.h:2462

NRF_SP_QSPI_Type::CONFIG
__IOM NRF_QSPI_CONFIG_Type CONFIG
Definition nrf_sp_qspi.h:2576

NRF_SP_QSPI_Type::INTPEND
__IM uint32_t INTPEND
Definition nrf_sp_qspi.h:2574

NRF_SP_QSPI_Type::ENABLE
__IOM uint32_t ENABLE
Definition nrf_sp_qspi.h:2575

NRF_SP_QSPI_Type::TASKS_START
__OM uint32_t TASKS_START
Definition nrf_sp_qspi.h:2563

NRF_SP_QSPI_Type::TASKS_RESET
__OM uint32_t TASKS_RESET
Definition nrf_sp_qspi.h:2564

NRF_SP_QSPI_Type::INTENCLR
__IOM uint32_t INTENCLR
Definition nrf_sp_qspi.h:2573

NRF_SP_QSPI_Type::SHORTS
__IOM uint32_t SHORTS
Definition nrf_sp_qspi.h:2570

NRF_SP_QSPI_Type::SPSYNC
__IOM NRF_QSPI_SPSYNC_Type SPSYNC
Definition nrf_sp_qspi.h:2580

NRF_SP_QSPI_Type::CORE
__IOM NRF_QSPI_CORE_Type CORE
Definition nrf_sp_qspi.h:2579

NRF_SP_QSPI_Type::DMA
__IOM NRF_QSPI_DMA_Type DMA
Definition nrf_sp_qspi.h:2578

NRF_SP_QSPI_Type::EVENTS_DMA
__IOM NRF_QSPI_EVENTS_DMA_Type EVENTS_DMA
Definition nrf_sp_qspi.h:2567

NRF_SP_QSPI_Type::INTENSET
__IOM uint32_t INTENSET
Definition nrf_sp_qspi.h:2572

NRF_SP_QSPI_Type::FORMAT
__IOM NRF_QSPI_FORMAT_Type FORMAT
Definition nrf_sp_qspi.h:2577

NRF_SP_QSPI_Type::INTEN
__IOM uint32_t INTEN
Definition nrf_sp_qspi.h:2571

NRF_SP_QSPI_Type::EVENTS_CORE
__IOM uint32_t EVENTS_CORE
Definition nrf_sp_qspi.h:2565

NRF_SP_QSPI_Type::EVENTS_IDLE
__IOM uint32_t EVENTS_IDLE
Definition nrf_sp_qspi.h:2568

NRF_SP_QSPI_Type
Quad serial peripheral interface.
Definition nrf_sp_qspi.h:2562