tx_bypass_pin_config

mpsl_fem_gpiote_pin_config_t mpsl_fem_simple_gpio_interface_config_t::tx_bypass_pin_config

TX bypass pin configuration.

GPIO used to select the Front End Module TX bypass path (lower gain/attenuated TX) as opposed to the PA path. Works together with fem_config.bypass_gain_db.

Bypass is active only when fem_config.bypass_gain_db is not 0 and mpsl_fem_gpiote_pin_config_t::enable is true. On nRF52 series (PPI) TX bypass is not supported.

When MPSL chooses bypass for a transmission, PA timing also drives this pin (activate and deactivate in parallel with pa_pin_config). When MPSL chooses the PA path, pa_pin_config alone is driven and this pin is left out of PA activation.

Same configuration as lna_pin_config: On some devices the TX bypass select shares the LNA control line. Set this field equal to lna_pin_config (same GPIO, active_high, enable, and gpiote_ch_id). The driver detects the shared pin and routes bypass GPIOTE tasks through the LNA tasks so hardware timing stays consistent.

Dedicated bypass GPIO: Use a different GPIO and GPIOTE channel than lna_pin_config and pa_pin_config. The driver toggles that line together with pa_pin_config only for bypass TX.

Same GPIO as pa_pin_config: Not supported for normal Front End Module wiring (PA and bypass are separate controls).