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Zephyr API 4.4.99
A Scalable Open Source RTOS
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Go to the source code of this file.
Macros | |
| #define | GD32_RCU_ADCCK_IRC28M_DIV2 0 |
| #define | GD32_RCU_ADCCK_IRC28M 1 |
| #define | GD32_RCU_ADCCK_APB2_DIV2 2 |
| #define | GD32_RCU_ADCCK_AHB_DIV3 3 |
| #define | GD32_RCU_ADCCK_APB2_DIV4 4 |
| #define | GD32_RCU_ADCCK_AHB_DIV5 5 |
| #define | GD32_RCU_ADCCK_APB2_DIV6 6 |
| #define | GD32_RCU_ADCCK_AHB_DIV7 7 |
| #define | GD32_RCU_ADCCK_APB2_DIV8 8 |
| #define | GD32_RCU_ADCCK_AHB_DIV9 9 |
| #define GD32_RCU_ADCCK_AHB_DIV3 3 |
| #define GD32_RCU_ADCCK_AHB_DIV5 5 |
| #define GD32_RCU_ADCCK_AHB_DIV7 7 |
| #define GD32_RCU_ADCCK_AHB_DIV9 9 |
| #define GD32_RCU_ADCCK_APB2_DIV2 2 |
| #define GD32_RCU_ADCCK_APB2_DIV4 4 |
| #define GD32_RCU_ADCCK_APB2_DIV6 6 |
| #define GD32_RCU_ADCCK_APB2_DIV8 8 |
| #define GD32_RCU_ADCCK_IRC28M 1 |
| #define GD32_RCU_ADCCK_IRC28M_DIV2 0 |