stm32f3_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x014
	Bus gatting clocks.
#define	STM32_CLOCK_BUS_APB2   0x018
#define	STM32_CLOCK_BUS_APB1   0x01c
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_PCLK   (STM32_SRC_HSI + 1)
	Bus clock.
#define	STM32_SRC_TIMPCLK1   (STM32_SRC_PCLK + 1)
#define	STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)
#define	STM32_SRC_TIMPLLCLK   (STM32_SRC_TIMPCLK2 + 1)
#define	STM32_SRC_PLLCLK   (STM32_SRC_TIMPLLCLK + 1)
	PLL clock.
#define	CFGR_REG   0x04
	RCC_CFGRx register offset.
#define	CFGR2_REG   0x2C
#define	CFGR3_REG   0x30
#define	BDCR_REG   0x20
	RCC_BDCR register offset.
#define	I2S_SEL(val)
	Device domain clocks selection helpers)
#define	MCO1_SEL(val)
#define	MCO1_PRE(val)
#define	ADC12_PRE(val)
	CFGR2 devices.
#define	ADC34_PRE(val)
#define	USART1_SEL(val)
	CFGR3 devices.
#define	I2C1_SEL(val)
#define	I2C2_SEL(val)
#define	I2C3_SEL(val)
#define	TIM1_SEL(val)
#define	TIM8_SEL(val)
#define	TIM15_SEL(val)
#define	TIM16_SEL(val)
#define	TIM17_SEL(val)
#define	TIM20_SEL(val)
#define	USART2_SEL(val)
#define	USART3_SEL(val)
#define	USART4_SEL(val)
#define	USART5_SEL(val)
#define	TIM2_SEL(val)
#define	TIM3_4_SEL(val)
#define	RTC_SEL(val)
	BDCR devices.
#define	ADC_PRE_DISABLED   0x0
#define	ADC_PRE_DIV_1   0x10
#define	ADC_PRE_DIV_2   0x11
#define	ADC_PRE_DIV_4   0x12
#define	ADC_PRE_DIV_6   0x13
#define	ADC_PRE_DIV_8   0x14
#define	ADC_PRE_DIV_10   0x15
#define	ADC_PRE_DIV_12   0x16
#define	ADC_PRE_DIV_16   0x17
#define	ADC_PRE_DIV_32   0x18
#define	ADC_PRE_DIV_64   0x19
#define	ADC_PRE_DIV_128   0x1A
#define	ADC_PRE_DIV_256   0x1B

Macro Definition Documentation

ADC12_PRE

#define ADC12_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 8, 4, CFGR2_REG)

CFGR2 devices.

ADC34_PRE

#define ADC34_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 13, 9, CFGR2_REG)

ADC_PRE_DISABLED

#define ADC_PRE_DISABLED   0x0

ADC_PRE_DIV_1

#define ADC_PRE_DIV_1   0x10

ADC_PRE_DIV_10

#define ADC_PRE_DIV_10   0x15

ADC_PRE_DIV_12

#define ADC_PRE_DIV_12   0x16

ADC_PRE_DIV_128

#define ADC_PRE_DIV_128   0x1A

ADC_PRE_DIV_16

#define ADC_PRE_DIV_16   0x17

ADC_PRE_DIV_2

#define ADC_PRE_DIV_2   0x11

ADC_PRE_DIV_256

#define ADC_PRE_DIV_256   0x1B

ADC_PRE_DIV_32

#define ADC_PRE_DIV_32   0x18

ADC_PRE_DIV_4

#define ADC_PRE_DIV_4   0x12

ADC_PRE_DIV_6

#define ADC_PRE_DIV_6   0x13

ADC_PRE_DIV_64

#define ADC_PRE_DIV_64   0x19

ADC_PRE_DIV_8

#define ADC_PRE_DIV_8   0x14

BDCR_REG

#define BDCR_REG   0x20

RCC_BDCR register offset.

CFGR2_REG

#define CFGR2_REG   0x2C

CFGR3_REG

#define CFGR3_REG   0x30

CFGR_REG

#define CFGR_REG   0x04

RCC_CFGRx register offset.

I2C1_SEL

#define I2C1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 4, 4, CFGR3_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 5, 5, CFGR3_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 6, 6, CFGR3_REG)

I2S_SEL

#define I2S_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 23, 23, CFGR_REG)

Device domain clocks selection helpers)

CFGR devices

MCO1_PRE

#define MCO1_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR_REG)

RTC_SEL

#define RTC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)

BDCR devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x014

Bus gatting clocks.

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x01c

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x018

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_HSI + 1)

Bus clock.

STM32_SRC_PLLCLK

#define STM32_SRC_PLLCLK   (STM32_SRC_TIMPLLCLK + 1)

PLL clock.

STM32_SRC_TIMPCLK1

#define STM32_SRC_TIMPCLK1   (STM32_SRC_PCLK + 1)

STM32_SRC_TIMPCLK2

#define STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)

STM32_SRC_TIMPLLCLK

#define STM32_SRC_TIMPLLCLK   (STM32_SRC_TIMPCLK2 + 1)

TIM15_SEL

#define TIM15_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 10, 10, CFGR3_REG)

TIM16_SEL

#define TIM16_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 11, 11, CFGR3_REG)

TIM17_SEL

#define TIM17_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR3_REG)

TIM1_SEL

#define TIM1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 8, 8, CFGR3_REG)

TIM20_SEL

#define TIM20_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 15, CFGR3_REG)

TIM2_SEL

#define TIM2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 24, 24, CFGR3_REG)

TIM3_4_SEL

#define TIM3_4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 25, 25, CFGR3_REG)

TIM8_SEL

#define TIM8_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 9, 9, CFGR3_REG)

USART1_SEL

#define USART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 0, CFGR3_REG)

CFGR3 devices.

USART2_SEL

#define USART2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 17, 16, CFGR3_REG)

USART3_SEL

#define USART3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 19, 18, CFGR3_REG)

USART4_SEL

#define USART4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 21, 20, CFGR3_REG)

USART5_SEL

#define USART5_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR3_REG)