MPSL Clock

The page describes the MPSL clock module design.

Overview

The MPSL requires access to both the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK) for its operation.

On the nRF52 Series, nRF53 Series, and nRF54L Series SoCs, the module provides access to the LFCLK configuration and allows the application to request the crystal oscillator source of the HFCLK. On the nRF54H Series SoCs, the module provides APIs to integrate the MPSL with an external clock driver.

See the following MPSL internal clock control and MPSL external clock control integration sections for descriptions of the design.

MPSL internal clock control

The internal clock control feature is available only for the nRF52 Series, nRF53 Series, and nRF54L Series SoCs.

Low-frequency clock (LFCLK)

MPSL can use one of the following available low-frequency clock (LFCLK) sources:

  • 32.768 kHz internal RC oscillator (LFRC)

  • 32.768 kHz crystal oscillator (LFXO)

When MPSL is enabled, the application must provide the selected LFCLK source, calibration configurations, and clock accuracy. The selected accuracy is meant to be forwarded only to the protocol stacks.

The MPSL clock module configures the LFCLK source and keeps it calibrated when the RC oscillator is the selected clock source.

Variations in temperature affect the RC oscillator frequency. As such, it requires additional calibration for temperature changes of more than 0.5°C.

To ensure the required accuracy, the MPSL clock module must calibrate periodically the RC oscillator using the HFCLK crystal oscillator as a reference. See the relevant SoC product specification for more information. As the MPSL clock module runs the calibration automatically, the application must specify how often the clock module takes measurements to detect temperature changes.

Note

You should consider how frequently significant temperature changes are expected to occur in the intended environment of the end product. It is recommended to use a temperature polling interval of 4 seconds, and to force the clock calibration every second interval (.rc_ctiv=16, .rc_temp_ctiv=2).

High-frequency clock (HFCLK)

The high-frequency clock (HFCLK) controller supports multiple sources, most notably the crystal oscillator (HFXO). On some platforms, there is also a 24 MHz peripheral clock (HFCLK24M) used for example by USB. See mpsl_clock_hfclk_src_t for the available clock sources.

The HFXO must be running to use the RADIO peripheral. MPSL makes sure the HFXO is started in time for every scheduled RADIO activity.

Note

For the correct operation of the RADIO peripheral, you must configure the HFXO startup time. See the MPSL_HFCLK_LATENCY Kconfig option for details on how to do this. As such, you must choose the external crystal oscillator and the other related components accordingly. See the relevant SoC product specification for more information.

The MPSL clock module API enables the application to safely request (mpsl_clock_hfclk_src_request()) and release (mpsl_clock_hfclk_src_release()) an HFCLK source while the protocol stacks are enabled. MPSL can continue to use the HFXO after it is released if it is requested by protocol stacks. HFXO is stopped when it is no longer needed.

MPSL external clock control integration

The MPSL clock module provides APIs to register the mpsl_clock_ctrl_source_register() and unregister the mpsl_clock_ctrl_source_unregister() external clock control driver. The call to mpsl_clock_ctrl_source_register() must be done before the mpsl_init() call, to have an effect. This API also enables the use of the external clock control by the MPSL. The call to mpsl_clock_ctrl_source_unregister() must be done after the mpsl_uninit() call.

Note

When you use the MPSL with external clock control feature, the MPSL internal clock control APIs are not allowed to be called.

APIs and data required for integration of MPSL with external clock control are provided by mpsl_clock_lfclk_ctrl_source_t for LFCLK and mpsl_clock_hfclk_ctrl_source_t for HFCLK.

Low-frequency clock (LFCLK) integration

It is the external clock control driver’s responsibility to configure the LFCLK source and keep it calibrated. On the nRF52 Series and nRF53 Series, the MPSL may initiate additional calibration events by using the lfclk_calibration_start() API.

The MPSL will defer waiting for LFCLK until it is used for the first time if skip_wait_lfclk_started is set to true.

The lfclk_request, lfclk_release, and lfclk_wait APIs are mandatory. The accuracy_ppm value is meant to be forwarded only to the protocol stacks.

High-frequency clock (HFCLK) integration

The HFXO must be running to use the RADIO peripheral.

Note

On the nRF54H Series SoC, the HFXO is required for the use of any peripheral located in the radio power domain in the radio core.

MPSL makes sure the HFXO is started in time for every scheduled RADIO activity. HFXO is stopped when it is no longer needed.

The hfclk_request, hfclk_release, and hfclk_is_running APIs are mandatory. These APIs will be called by MPSL from high priority, so they may not use blocking operations.

You must correctly configure the startup_time_us for the RADIO operation. See the MPSL_HFCLK_LATENCY Kconfig option for details on how to do this. As such, you must choose the external crystal oscillator and the other related components accordingly. See the relevant SoC product specification for more information.