sQSPI limitations

When working with sQSPI, you should be aware of the following limitations.

v1.2.1

Refer to the following detailed descriptions of current limitations:

• sQSPI does not support slave mode operations; it can only operate as a controller (master).

• The sQSPI support for SPI half-duplex setup is implemented but not tested.

• sQSPI SPI modes 1,2, and 3 (see the nrf_sqspi_dev_cfg_t.spi_cpolpha configuration structure) may present artifacts (clock stretching or extra edges) on the last SCLK cycle during a read. This has no effect on data integrity.

• The nrfx API for sQSPI does not support configuring the use of the positive or negative edge of SCLK delayed read sampling.

• sQSPI employs the nrf_sqspi_dev_cfg_t.sample_delay_cyc parameter as an offset to FLPR’s base clock counter , not SLCK clock cycles (see the nrf_sqspi_dev_cfg_t struct).

• sQSPI nrf_sqspi_dev_cfg_t.sample_delay_cyc is constrained to either a value of 0 if using GPIOHSPADCTRL for high-speed transfers (see High speed transfers) or a value greater than 0 but lower than that of FLPR_counter if a high-speed transfer is not needed (see sQSPI and FLPR counters).

• Implementation of sQSPI quad or dual lane for command transmission (for example, 2_2_2 and 4_4_4 modes) is implemented but has not been tested.

• sQSPI does not support a configurable pin for the CSN line; only PIN 5 is supported (see nrf_sqspi_dev_cfg_t.csn_pin).

• nrf_sqspi_xfer_t.p_data needs to be a pointer with a 32-bit aligned address.

• sQSPI high-speed reading cannot happen directly when changing from SPI mode 0 to 3. Either do a high-speed write or a slow read (5.8 MHz) in between.

• nrf_sqspi_xfer_t.addr_length must be greater than nrf_sqspi_dev_cfg_t.mspi_lines.

• Any prepared transfer with nrf_sqspi_xfer_prepare() will be discarded when using nrf_sqspi_deactivate().

• sQSPI will present undefined behavior in the following cases:

  • 0 byte reads: nrf_sqspi_xfer_t.dir set to NRF_SQSPI_XFER_DIR_RX and nrf_sqspi_xfer_t.data_length set to 0.

  • 0 command bits: nrf_sqspi_xfer_t.cmd_length set to 0.

  • 0 address bits: nrf_sqspi_xfer_t.addr_length set to 0.

Data format (display use) limitations:

• nrf_sqspi_data_fmt_t.data_bit_reorder_unit must be set to the same value as nrf_sqspi_data_fmt_t.data_swap_unit.

• If nrf_sqspi_data_fmt_t.data_padding is not set to 0 - Sum of nrf_sqspi_data_fmt_t.data_container and nrf_sqspi_data_fmt_t.data_padding must be equal to 32.

• Combination of nrf_sqspi_data_fmt_t.data_padding equal to 24 and nrf_sqspi_data_fmt_t.data_swap_unit equal to 8, when clkdiv is equal to or less than 6 (see sQSPI and FLPR counters) and nrf_sqspi_dev_cfg_t.mspi_lines is NRF_SQSPI_SPI_LINES_DUAL_X_Y_2 or NRF_SQSPI_SPI_LINES_QUAD_X_Y_4, leads to the wrong frequency on SCLK.

• The value calculated as: 32 - nrf_sqspi_data_fmt_t.data_padding must be a multiple of nrf_sqspi_data_fmt_t.data_swap_unit.

• nrf_sqspi_data_fmt_t.data_swap_unit values 0 and 4 are not supported.

• nrf_sqspi_data_fmt_t.data_bit_order and nrf_sqspi_data_fmt_t.addr_bit_order do not support the value: NRF_SQSPI_DATA_FMT_BIT_ORDER_LSB_FIRST.