SPI Manager

The SPI manager sample demonstrates how to use the SPI transaction manager library with nRF Connect SDK Bare Metal option to perform read, page program, and sector erase operations on the external flash memory of the development kit.

Requirements

The sample supports the following development kits with on-board SPI external flash:

The following board variants do not have DFU capabilities:

S115:

Hardware platform

PCA

Board target

nRF54L15 DK

PCA10156

bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice

nRF54L15 DK (emulating nRF54L10)

PCA10156

bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice

nRF54L15 DK (emulating nRF54L05)

PCA10156

bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice

nRF54LM20 DK

PCA10184

bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice

S145:

Hardware platform

PCA

Board target

nRF54L15 DK

PCA10156

bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice

nRF54L15 DK (emulating nRF54L10)

PCA10156

bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice

nRF54L15 DK (emulating nRF54L05)

PCA10156

bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice

nRF54LM20 DK

PCA10184

bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice

Note

The nRF54LV10 DK and nRF54LS05 DK do not have on-board external flash memory and are out of scope for this sample. However, the SPI transaction manager library itself is fully supported on the nRF54LV10 and nRF54LS05 SoCs. You can still use the SPI manager feature on these boards by connecting an external SPI target device (for example, an external NOR flash) to the SPI pins of the SoC and adapting the sample configuration accordingly (pin assignments in the board-config.h file, command set, and timing parameters to match your device).

Important

Before flashing the sample, you must enable External memory using the Board Configurator app in nRF Connect for Desktop, and then write the configuration to the board. Otherwise, the on-board flash is not powered or routed to the SoC, and the sample will not work.

Overview

The sample uses the SPI manager library to schedule read, program, and erase operations on the external flash. All operations target the same flash address (set by the CONFIG_SAMPLE_SPI_MNGR_FLASH_ADDR Kconfig option) and share a single SPI manager instance.

The flash is the on-board MX25-class NOR device on the development kit. Its SPI pins and strap pins that configure fixed hardware settings, such as write-protect and reset state at power on, are defined by the BOARD_EXTERNAL_MEMORY_* macros in the board-config.h file.

Configuration

You can modify the following options (available in the Kconfig file at samples/peripherals/spi_mngr/Kconfig):

  • CONFIG_SAMPLE_SPI_MNGR_MSG - Sets the message written to the external flash on program.

  • CONFIG_SAMPLE_SPI_MNGR_READ_LEN - Sets the number of bytes read from the external flash on read.

  • CONFIG_SAMPLE_SPI_MNGR_FLASH_ADDR - Sets the external flash address targeted by read, program, and erase. Keep it a multiple of 0x1000 (4 KiB sector size) to avoid a wrapped, corrupted write.

User interface

LED 0:

Lit when the device is initialized.

Button 1:

Erase external memory.

Button 2:

Read external memory.

Button 3:

Program external memory.

Building and running

This sample can be found under samples/peripherals/spi_mngr/ in the Bare Metal folder structure.

For details on how to create, configure, and program a sample, see Getting Started with the samples.

Testing

You can test this sample by performing the following steps:

  1. Compile and program the application.

  2. Observe that the SPI manager sample initialized message is printed, followed by the list of available buttons and their operations.

  3. Press Button 2 to read the on-board flash. The hex dump shows either all 0xFF (erased) or the data last written to the address.

  4. Press Button 3 to program the configured message (set with CONFIG_SAMPLE_SPI_MNGR_MSG, default Hello World!). The log prints Programming "Hello World!" @ 0x00100000.

  5. Press Button 2 again. The hex dump now starts with the message bytes, confirming the write succeeded. For the default configuration, this is 48 65 6c 6c 6f 20 57 6f 72 6c 64 21 (ASCII for Hello World!), followed by 0xFF padding.

  6. Power-cycle the board and press Button 2. The same message reappears, confirming the data persists across power cycles.

  7. Press Button 1 to erase the sector and wait for the self-timed erase to complete.

  8. Power-cycle the board again and press Button 2. The hex dump shows all 0xFF, confirming the erase succeeded.