FRDM-MCXA577

Overview

FRDM-MCXA577 is a compact and scalable development board for rapid prototyping of MCX A577 MCUs. They offer industry standard headers for easy access to the MCUs input/output (I/O), integrated open-standard serial interfaces, external flash memory and an onboard MCU-Link debugger.

Hardware

  • MCX-A577 Arm Cortex-M33 microcontroller running at 12MHz

  • 2048KB dual-bank on chip Flash

  • 640 KB RAM

  • 2x FlexCAN with FD, 1x RGB LED, 3x SW buttons

  • On-board MCU-Link debugger with CMSIS-DAP

  • Arduino Header, SmartDMA/Camera Header, mikroBUS

For more information about the MCX-A577 SoC and FRDM-MCXA577 board, see:

Supported Features

The frdm_mcxa577 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Shields for Supported Features

Some features in the table above are tested with Zephyr shields. These shields are tested on this board:

  • NXP LCD_PAR_S035 TFT LCD Module - supports the Display interface. This board uses the MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral.

Connections and IOs

The MCX-A577 SoC has 5 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name

Function

Usage

PIO0_2

UART

UART RX

PIO0_3

UART

UART TX

System Clock

The MCX-A577 SoC is configured to use FRO LF running at 12MHz as a source for the system clock.

Serial Port

The FRDM-MCXA577 SoC has 6 LPUART interfaces for serial communication. LPUART0 is configured as UART for the console.

Programming and Debugging

The frdm_mcxa577 board supports the runners and associated west commands listed below.

flash debug

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in ISP mode to program the firmware, short jumper JP4.

Configuring a Console

Connect a USB cable from your PC to J13, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa577 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa577/mcxa577

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa577/mcxa577 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa577/mcxa577

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.

Support Resources for Zephyr