FRDM-MCXE31B

Overview

The FRDM-MCXE31B board is a design and evaluation platform based on the NXP MCXE31B microcontroller (MCU). NXP MCXE31B MCU based on an Arm Cortex-M7 core, running at speeds of up to 160 MHz with a 2.97 to 5.5V supply.

Hardware

  • MCXE31B Arm Cortex-M7 microcontroller running up to 160 MHz

  • 4MB dual-bank on chip Flash

  • 320KB SRAM + 192KB TCM

  • 2x I2C

  • 6x SPI

  • 16x UART

  • On-board MCU-Link debugger with CMSIS-DAP

  • Arduino Header, mikroBUS

For more information about the MCXE31B SoC and FRDM-MCXE31B board, see:

Supported Features

The frdm_mcxe31b board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Shields for Supported Features

Some features in the table above are tested with Zephyr shields. These shields are tested on this board:

  • NXP LCD_PAR_S035 TFT LCD Module - supports the Display interface. This board uses the MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral.

Connections and IOs

Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high bank, from pin 16 to 31. For example, PTA2 is the pin 2 of gpioa_l (low bank), and PTA20 is the pin 4 of gpioa_h (high bank).

The GPIO controller provides the option to route external input pad interrupts to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, unless they are explicitly configured to be directed to the WKPU interrupt controller, as outlined in dts/bindings/gpio/nxp,siul2-gpio.yaml.

To find information about which GPIOs are compatible with each interrupt controller, refer to the device reference manual.

Name

Function

Usage

PTC16

GPIO

Red LED

PTB22

GPIO

Green LED

PTC14

GPIO

Blue LED

PTE3

LPUART5_RX

UART Console

PTE14

LPUART5_TX

UART Console

PTA7

FLEXCAN0

CAN0 TX

PTA6

FLEXCAN0

CAN0 RX

System Clock

The MCXE31B SoC is configured to use PLL running at 160MHz as a source for the system clock.

Serial Port

The MCXE31B LPUART5 is used for the console.

Programming and Debugging

The frdm_mcxe31b board supports the runners and associated west commands listed below.

flash debug

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in ISP mode to program the firmware, short jumper JP3.

Configuring a Console

Connect a USB cable from your PC to J13, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxe31b samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
Hello World! frdm_mcxe31b/mcxe31b

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxe31b samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
Hello World! frdm_mcxe31b/mcxe31b

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.

Support Resources for Zephyr