PSOC™ 4100S Max pioneer kit

Overview

The CY8CKIT-041S-MAX is a pioneer kit based on the PSOC™ 4100S Max family, featuring a PSOC™ 4100S Max (CY8C4149AZI_S598) microcontroller with an Arm® Cortex®-M0+ core running at up to 48 MHz. It is designed for capacitive touch sensing and general-purpose embedded applications.

Key features include 384 KB flash, 32 KB SRAM, CAPSENSE™ buttons, touchpad, slider, and proximity sensing, a thermistor, and an onboard KitProg3 programmer/debugger with USB Micro-B connectivity.

Hardware

  • SoC: PSOC™ 4100S Max (CY8C4149AZI_S598)

  • CPU: Arm® Cortex®-M0+ at 48 MHz

  • Flash: 384 KB

  • SRAM: 32 KB

  • Peripherals: SAR ADC, TCPWM, SCB (UART/SPI/I2C)

  • Touch Sensing: CAPSENSE™ buttons, touchpad, slider, and proximity sensing

  • Sensors: Thermistor for temperature measurement

  • Debug: Onboard KitProg3 (SWD + UART bridge)

  • Power: USB powered via Micro-B connector (5V operating)

For more information about the PSOC™ 4100S Max and CY8CKIT-041S-MAX:

Kit Contents

  • PSOC™ 4100S Max Pioneer Kit board

  • CAPSENSE™ expansion board

  • USB-A to Micro-B cable

  • 6 jumper wires

  • 40-pin FFC cable

  • Quick start guide

Supported Features

The cy8ckit_041s_max board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Connections and IOs

LEDs

Name

GPIO Pin

LED0

P7.3 (active low)

Default Zephyr Peripheral Mapping

Pin

Function

Usage

P0.5

SCB2 UART TX

Console TX

P0.4

SCB2 UART RX

Console RX

P7.3

GPIO

LED0

System Clock

The PSOC™ 4100S Max uses the Internal Main Oscillator (IMO) as the default system clock source. The clock path is:

  • IMO (Internal Main Oscillator): 48 MHz

  • CLK_HF: 48 MHz (system clock)

Serial Port

The PSOC™ 4100S Max has multiple SCB (Serial Communication Block) interfaces that can be configured as UART, SPI, or I2C. The Zephyr console output is assigned to SCB2 (uart2), which is routed through the KitProg3 USB-UART bridge.

Default communication settings are 115200 8N1.

Building

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b cy8ckit_041s_max samples/hello_world

Programming and Debugging

The cy8ckit_041s_max board supports the runners and associated west commands listed below.

flash debug

The CY8CKIT-041S-MAX includes an onboard programmer/debugger (KitProg3) which can be used to program and debug the PSOC™ 4100S Max Cortex-M0+ core.

Infineon OpenOCD Installation

The ModusToolbox™ Programming Tools package includes Infineon OpenOCD. Alternatively, a standalone installation can be done by downloading the Infineon OpenOCD release for your system and extracting the files to a location of your choice.

Note

Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox™ Programming Tools installation. When doing a standalone OpenOCD installation, this can be done manually by executing the script openocd/udev_rules/install_rules.sh.

Configuring a Console

Connect a USB cable from your PC to the KitProg3 USB Micro-B connector (J8) on the CY8CKIT-041S-MAX.Use the serial terminal of your choice (minicom, PuTTY, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

One time, set the Infineon OpenOCD path:

west config build.cmake-args -- "-DOPENOCD=path/to/infineon/openocd/bin/openocd.exe"

Build and flash the application:

west build -b cy8ckit_041s_max -p always samples/hello_world
west flash

You should see the following message on the console:

*** Booting Zephyr OS build vX.Y.Z ***
Hello World! cy8ckit_041s_max

Debugging

# From the root of the zephyr repository
west build -b cy8ckit_041s_max samples/hello_world
west debug

Once the GDB console starts, you may set breakpoints and perform standard GDB debugging on the PSOC™ 4100S Max Cortex-M0+ core.

References