RA8P1 Evaluation Kit

Overview

The EK-RA8P1 is an Evaluation Kit for Renesas RA8P1 MCU Group which integrates multiple series of software-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® Cortex®-M33 core running up to 250 MHz with the following features:

  • Up to 1 MB MRAM

  • 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)

  • Arm® Ethos™-U55 NPU

  • Octal Serial Peripheral Interface (OSPI)

  • Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface

  • Graphics LCD Controller (GLCDC)

  • 2D Drawing Engine (DRW)

  • MIPI DSI/CSI interface

  • Analog peripherals

  • Security and safety features

MCU Native Pin Access

  • 1 GHz Arm Cortex-M85 and 250 MHz Arm Cortex-M33 based RA8P1 MCU in 289 pins, BGA package

  • Native pin access through 2 x 20-pin, and 2 x 40-pin headers (no populated)

  • Camera Expansion connector (present on the underside of the EK-RA8P1 board)

  • 2-Lane MIPI Display connector (present on the underside of the EK-RA8P1 board)

  • Parallel graphics display interface connector

  • MCU current measurement points for precision current consumption measurement

  • Multiple clock sources - RA8P1 MCU oscillator and sub-clock oscillator crystals, providing precision 24.000 MHz and 32,768 Hz reference clocks. Additional low precision clocks are available internal to the RA8P1 MCU

System Control and Ecosystem Access

  • USB Full Speed Host and Device (USB-C connector)

  • Four 5V input sources

    • USB (Debug, Full Speed, High Speed)

    • External power supply (using surface mount clamp test points and power input vias)

  • Three Debug modes

    • Debug on-board (SWD and JTAG)

    • Debug in (ETM, SWD, SWO and JTAG)

    • Debug out (SWD, SWO, and JTAG)

  • User LEDs and buttons

    • Three User LEDs (red, blue, green)

    • Power LED (white) indicating availability of regulated power

    • Debug LED (yellow) indicating the debug connection

    • Ethernet LEDs (amber, yellow, green)

    • Two User buttons

    • One Reset button

  • Five most popular ecosystems expansions

    • Two Seeed Grove system (I2C/I3C/Analog) connectors (not populated)

    • One SparkFun Qwiic connector (not populated)

    • Two Digilent Pmod (SPI, UART and I2C) connectors

    • Arduino (Uno R3) connector

    • MikroElektronika mikroBUS connector (not populated)

  • MCU boot configuration jumper

Special Feature Access

  • Ethernet (RJ45 RGMII interface)

  • USB High Speed Host and Device (USB-C connector)

  • 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8P1 board)

Hardware

Detailed hardware features can be found at:

Supported Features

The ek_ra8p1 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Note

  • For using the Camera Expansion Port (J35) in DVP interface, please set switch SW4 as following configuration:

    SW4-1 PMOD1

    SW4-2 PMOD1

    SW4-3 Octo-SPI

    SW4-4 Arduino

    SW4-5 I3C

    SW4-6 MIPI

    SW4-7 USBFS

    SW4-8 USBHS

    OFF

    OFF

    OFF

    OFF

    OFF

    ON

    OFF

    OFF

Dual Core Operation

The EK-RA8P1 supports dual core operation with both the Cortex-M85 (CPU0) and Cortex-M33 (CPU1) cores. By default, the CM85 core is the boot core and is responsible for initializing the system and starting the CM33 core.

Memory Usage

By default, MRAM (Flash) and SRAM are split evenly between the two cores. Users can manually change the address and size for MRAM (Flash) and SRAM as follows node:

  • CPU0: &code_mram_cm85, &sram0

  • CPU1: &code_mram_cm33, &sram1

Note

  • MRAM usable range: 0x0200_0000 … 0x0210_0000 (1 MB)

  • SRAM usable range: 0x2200_0000 … 0x221A_0000 (1664 KB)

Dual Core Flashing

When flashing or debugging dual-core samples, ensure that CONFIG_SOC_RA_ENABLE_START_SECOND_CORE is selected for the CM85 image. The CM85 core is responsible for starting the CM33 core in soc_late_init_hook.

Programming and Debugging

The ek_ra8p1 board supports the runners and associated west commands listed below.

flash debug

Applications for the ek_ra8p1 board configuration can be built, flashed, and debugged in the usual way. See Building an Application and Run an Application for more details on building and running.

Here is an example for the Hello World application on CM85 core.

# From the root of the zephyr repository
west build -b ek_ra8p1/r7ka8p1kflcac/cm85 samples/hello_world
west flash

Open a serial terminal, reset the board (press the S3 button), and you should see the following message in the terminal:

***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx *****
Hello World! ek_ra8p1/r7ka8p1kflcac/cm85

For the CM33 core, you can use the --sysbuild flow to build a minimal first-core launcher image that starts the CM33 core.

# From the root of the zephyr repository
west build -b ek_ra8p1/r7ka8p1kflcac/cm33 --sysbuild samples/hello_world
west flash

Flashing

Program can be flashed to EK-RA8P1 via the on-board SEGGER J-Link debugger. SEGGER J-link’s drivers are available at https://www.segger.com/downloads/jlink/

To flash the program to board

  1. Connect to J-Link OB via USB port to host PC

  2. Make sure J-Link OB jumper is in default configuration as described in EK-RA8P1 - User’s Manual

  3. Execute west command

    west flash -r jlink

MCUboot bootloader

The sysbuild makes possible to build and flash all necessary images needed to bootstrap the board.

To build the sample application using sysbuild use the command:

# From the root of the zephyr repository
west build -b ek_ra8p1/r7ka8p1kflcac/cm85 --sysbuild samples/hello_world -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
west flash

By default, Sysbuild creates MCUboot and user application images.

Build directory structure created by sysbuild is different from traditional Zephyr build. Output is structured by the domain subdirectories:

build/
├── hello_world
|    └── zephyr
│       ├── zephyr.elf
│       ├── zephyr.hex
│       ├── zephyr.bin
│       ├── zephyr.signed.bin
│       └── zephyr.signed.hex
├── mcuboot
│    └── zephyr
│       ├── zephyr.elf
│       ├── zephyr.hex
│       └── zephyr.bin
└── domains.yaml

Note

With --sysbuild option, MCUboot will be rebuilt and re-flashed every time the pristine build is used.

To only flash the user application in the subsequent builds, Use:

$ west flash --domain hello_world

For more information about the system build please read the Sysbuild (System build) documentation.

You should see the following message in the terminal:

*** Booting MCUboot v2.2.0-171-g8513be710e5e ***
*** Using Zephyr OS build v4.2.0-6156-ged85ac9ffda9 ***
I: Starting bootloader
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x10000
I: Image version: v0.0.0
I: Jumping to the first image slot
*** Booting Zephyr OS build v4.2.0-6156-ged85ac9ffda9 ***
Hello World! ek_ra8p1/r7ka8p1kflcac/cm85

References