Glyph-C6

Overview

Glyph-C6 is powered by ESP32-C6 SoC. It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. It has a 512KB SRAM, and works with 4MB external SPI flash. For more information, check Glyph-C6 [6].

Hardware

Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount glyph c6 on a breadboard.

ESP32-C6 Features

ESP32-C6 is Espressif’s first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the 802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security features and multiple memory resources for IoT products. It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. It has a 320KB ROM, a 512KB SRAM, and works with external flash.

ESP32-C6 includes the following features:

  • 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz

  • 400 KB of internal RAM

  • WiFi 802.11 ax 2.4GHz

  • Fully compatible with IEEE 802.11b/g/n protocol

  • Bluetooth LE: Bluetooth 5.3 certified

  • Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna

  • IEEE 802.15.4 (Zigbee and Thread)

Digital interfaces:

  • 30x GPIOs (QFN40), or 22x GPIOs (QFN32)

  • 2x UART

  • 1x Low-power (LP) UART

  • 1x General purpose SPI

  • 1x I2C

  • 1x Low-power (LP) I2C

  • 1x I2S

  • 1x Pulse counter

  • 1x USB Serial/JTAG controller

  • 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)

  • 1x SDIO 2.0 slave controller

  • LED PWM controller, up to 6 channels

  • 1x Motor control PWM (MCPWM)

  • 1x Remote control peripehral

  • 1x Parallel IO interface (PARLIO)

  • General DMA controller (GDMA), with 3 transmit channels and 3 receive channels

  • Event task matrix (ETM)

Analog interfaces:

  • 1x 12-bit SAR ADCs, up to 7 channels

  • 1x temperature sensor

Timers:

  • 1x 52-bit system timer

  • 1x 54-bit general-purpose timers

  • 3x Watchdog timers

  • 1x Analog watchdog timer

Low Power:

  • Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep

Security:

  • Secure boot

  • Flash encryption

  • 4-Kbit OTP, up to 1792 bits for users

  • Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash)

  • Random number generator (RNG)

Low-Power CPU (LP CORE)

The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE). The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus interface for memory and peripheral access.

The LP Core is in sleep mode by default. It has two application scenarios:

  • Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations.

  • Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.

The LP Core support is fully integrated with Sysbuild (System build). The user can enable the LP Core by adding the following configuration to the project:

CONFIG_ESP32_ULP_COPROC_ENABLED=y

See Low-Power CPU (LP CORE) folder as code reference.

For more information, check the ESP32-C6 Datasheet [1] or the ESP32-C6 Technical Reference Manual [2].

Supported Features

The glyph_c6 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

System Requirements

Binary Blobs

Espressif HAL requires RF binary blobs in order work. Run the command below to retrieve those files.

west blobs fetch hal_espressif

Note

It is recommended running the command above after west update.

Programming and Debugging

The glyph_c6 board supports the runners and associated west commands listed below.

flash debug

Simple Boot

The board could be loaded using the single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration.

Note

Simple boot does not provide any security features nor OTA updates.

MCUboot Bootloader

User may choose to use MCUboot bootloader instead. In that case the bootloader must be built (and flashed) at least once.

There are two options to be used when building an application:

  1. Sysbuild

  2. Manual build

Note

User can select the MCUboot bootloader by adding the following line to the board default configuration file.

CONFIG_BOOTLOADER_MCUBOOT=y

Sysbuild

The sysbuild makes possible to build and flash all necessary images needed to bootstrap the board with the ESP32 SoC.

To build the sample application using sysbuild use the command:

west build -b <board> --sysbuild samples/hello_world

By default, the ESP32 sysbuild creates bootloader (MCUboot) and application images. But it can be configured to create other kind of images.

Build directory structure created by sysbuild is different from traditional Zephyr build. Output is structured by the domain subdirectories:

build/
├── hello_world
│   └── zephyr
│       ├── zephyr.elf
│       └── zephyr.bin
├── mcuboot
│    └── zephyr
│       ├── zephyr.elf
│       └── zephyr.bin
└── domains.yaml

Note

With --sysbuild option the bootloader will be re-build and re-flash every time the pristine build is used.

For more information about the system build please read the Sysbuild (System build) documentation.

Manual Build

During the development cycle, it is intended to build & flash as quickly possible. For that reason, images can be built one at a time using traditional build.

The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory.

Note

Remember that bootloader (MCUboot) needs to be flash at least once.

Build and flash applications as usual (see Building an Application and Run an Application for more details).

# From the root of the zephyr repository
west build -b <board> samples/hello_world

The usual flash target will work with the board configuration. Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b <board> samples/hello_world
west flash

Open the serial monitor using the following command:

west espressif monitor

After the board has automatically reset and booted, you should see the following message in the monitor:

***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! <board>

Board variants using Snippets

ESP32 boards can be assembled with different modules using multiple combinations of SPI flash sizes, PSRAM sizes and PSRAM modes. The snippets under snippets/espressif provide a modular way to apply these variations at build time without duplicating board definitions.

The following snippet-based variants are supported:

Snippet name

Description

Flash memory size

espressif-flash-4M

Board with 4MB of flash

espressif-flash-8M

Board with 8MB of flash

espressif-flash-16M

Board with 16MB of flash

espressif-flash-32M

Board with 32MB of flash

espressif-flash-64M

Board with 64MB of flash

espressif-flash-128M

Board with 128MB of flash

PSRAM memory size

espressif-psram-2M

Board with 2MB of PSRAM

espressif-psram-4M

Board with 4MB of PSRAM

espressif-psram-8M

Board with 8MB of PSRAM

PSRAM utilization

espressif-psram-reloc

Relocate flash to PSRAM

espressif-psram-wifi

Wi-Fi buffers in PSRAM

To apply a board variant, use the -S flag with west build:

west build -b <board> -S espressif-flash-32M -S espressif-psram-4M samples/hello_world

Note

These snippets are only applicable to boards with compatible hardware support for the selected flash/PSRAM configuration.

  • If no FLASH snippet is used, the board default flash size will be used.

  • If no PSRAM snippet is used, the board default psram size will be used.

Debugging

OpenOCD Debugging

Espressif chips require a custom OpenOCD build with ESP32-specific patches. Download the latest release from OpenOCD for ESP32 [3].

For detailed JTAG setup instructions, see JTAG debugging for ESP32 [5].

Zephyr Thread Awareness

OpenOCD supports Zephyr RTOS thread awareness, allowing GDB to:

  • List all threads with info threads

  • Display thread names, priorities, and states

  • Switch between thread contexts

  • Show backtraces for any thread

Requirements:

Example:

# From the root of the zephyr repository
west build -b <board> samples/hello_world -- -DCONFIG_DEBUG_THREAD_INFO=y -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
west debug

Using a Custom OpenOCD

The Zephyr SDK includes a bundled OpenOCD, but it may not have ESP32 support. To use the Espressif OpenOCD, specify the path when building:

# From the root of the zephyr repository
west build -b <board> samples/hello_world -- -DOPENOCD=/path/to/openocd -DOPENOCD_DEFAULT_PATH=/path/to/openocd/scripts
west debug

References