AMD Zynq UltraScale+ MPSoC RPU

Overview

This board configuration targets the Cortex-R5 real-time processing unit (RPU) on AMD Zynq UltraScale+ MPSoC. R5 DDR starts at 0x00400000, GIC for the RPU is at 0xf9000000, and PS UART0 is at 0xff000000.

Hardware

Supported Features

The zynqmp_rpu board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

The default console is UART0 (typical Linux name ttyPS0).

Memories

  • sram0 is at 0x0400_0000 (64 MiB).

  • QSPI linear flash is mapped at 0xc0000000 (512 MiB).

Known limitations

  • Dual-redundant lock-step R5 operation is not targeted by this board file.

  • Only the first R5 core is supported.

Programming and Debugging

The zynqmp_rpu board supports the runners and associated west commands listed below.

flash debug

QEMU

The board uses the arm-generic-fdt QEMU machine with a ZCU102 hardware DTB compiled from zynqmp_rpu-qemu.dts at build time. The Zephyr ELF is loaded on cpu-num=4 (the R5 cluster); MMIO pokes at 0xff5e023c and 0xff9a0000 release the R5 from reset.

west build -b zynqmp_rpu samples/hello_world
west build -t run

Hardware (XSDB)

# From the root of the zephyr repository
west build -b zynqmp_rpu samples/hello_world

References

  1. AMD Zynq UltraScale+ Device Technical Reference Manual (UG1085)